Texas Instruments
LM3S9997
2024.06.02
ARM Cortex-M3 Stellaris Device
false
8
32
ADC0
Register map for ADC0 peripheral
ADC
0x0
0x0
0x1000
registers
n
ACTSS
ADC Active Sample Sequencer
0x0
-1
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0ACTSS
ADC Active Sample Sequencer
0x0
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0CTL
ADC Control
0x38
read-write
n
0x0
0x0
ADC_CTL_VREF
Voltage Reference Select
0
1
ADC0DCCMP0
ADC Digital Comparator Range 0
0xE40
read-write
n
0x0
0x0
ADC_DCCMP0_COMP0
Compare 0
0
10
ADC_DCCMP0_COMP1
Compare 1
16
26
ADC0DCCMP1
ADC Digital Comparator Range 1
0xE44
read-write
n
0x0
0x0
ADC_DCCMP1_COMP0
Compare 0
0
10
ADC_DCCMP1_COMP1
Compare 1
16
26
ADC0DCCMP2
ADC Digital Comparator Range 2
0xE48
read-write
n
0x0
0x0
ADC_DCCMP2_COMP0
Compare 0
0
10
ADC_DCCMP2_COMP1
Compare 1
16
26
ADC0DCCMP3
ADC Digital Comparator Range 3
0xE4C
read-write
n
0x0
0x0
ADC_DCCMP3_COMP0
Compare 0
0
10
ADC_DCCMP3_COMP1
Compare 1
16
26
ADC0DCCMP4
ADC Digital Comparator Range 4
0xE50
read-write
n
0x0
0x0
ADC_DCCMP4_COMP0
Compare 0
0
10
ADC_DCCMP4_COMP1
Compare 1
16
26
ADC0DCCMP5
ADC Digital Comparator Range 5
0xE54
read-write
n
0x0
0x0
ADC_DCCMP5_COMP0
Compare 0
0
10
ADC_DCCMP5_COMP1
Compare 1
16
26
ADC0DCCMP6
ADC Digital Comparator Range 6
0xE58
read-write
n
0x0
0x0
ADC_DCCMP6_COMP0
Compare 0
0
10
ADC_DCCMP6_COMP1
Compare 1
16
26
ADC0DCCMP7
ADC Digital Comparator Range 7
0xE5C
read-write
n
0x0
0x0
ADC_DCCMP7_COMP0
Compare 0
0
10
ADC_DCCMP7_COMP1
Compare 1
16
26
ADC0DCCTL0
ADC Digital Comparator Control 0
0xE00
read-write
n
0x0
0x0
ADC_DCCTL0_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL0_CIC_LOW
Low Band
0x0
ADC_DCCTL0_CIC_MID
Mid Band
0x1
ADC_DCCTL0_CIC_HIGH
High Band
0x3
ADC_DCCTL0_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL0_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL0_CIM_ALWAYS
Always
0x0
ADC_DCCTL0_CIM_ONCE
Once
0x1
ADC_DCCTL0_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL0_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL0_CTC_LOW
Low Band
0x0
ADC_DCCTL0_CTC_MID
Mid Band
0x1
ADC_DCCTL0_CTC_HIGH
High Band
0x3
ADC_DCCTL0_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL0_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL0_CTM_ALWAYS
Always
0x0
ADC_DCCTL0_CTM_ONCE
Once
0x1
ADC_DCCTL0_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL1
ADC Digital Comparator Control 1
0xE04
read-write
n
0x0
0x0
ADC_DCCTL1_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL1_CIC_LOW
Low Band
0x0
ADC_DCCTL1_CIC_MID
Mid Band
0x1
ADC_DCCTL1_CIC_HIGH
High Band
0x3
ADC_DCCTL1_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL1_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL1_CIM_ALWAYS
Always
0x0
ADC_DCCTL1_CIM_ONCE
Once
0x1
ADC_DCCTL1_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL1_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL1_CTC_LOW
Low Band
0x0
ADC_DCCTL1_CTC_MID
Mid Band
0x1
ADC_DCCTL1_CTC_HIGH
High Band
0x3
ADC_DCCTL1_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL1_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL1_CTM_ALWAYS
Always
0x0
ADC_DCCTL1_CTM_ONCE
Once
0x1
ADC_DCCTL1_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL2
ADC Digital Comparator Control 2
0xE08
read-write
n
0x0
0x0
ADC_DCCTL2_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL2_CIC_LOW
Low Band
0x0
ADC_DCCTL2_CIC_MID
Mid Band
0x1
ADC_DCCTL2_CIC_HIGH
High Band
0x3
ADC_DCCTL2_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL2_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL2_CIM_ALWAYS
Always
0x0
ADC_DCCTL2_CIM_ONCE
Once
0x1
ADC_DCCTL2_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL2_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL2_CTC_LOW
Low Band
0x0
ADC_DCCTL2_CTC_MID
Mid Band
0x1
ADC_DCCTL2_CTC_HIGH
High Band
0x3
ADC_DCCTL2_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL2_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL2_CTM_ALWAYS
Always
0x0
ADC_DCCTL2_CTM_ONCE
Once
0x1
ADC_DCCTL2_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL3
ADC Digital Comparator Control 3
0xE0C
read-write
n
0x0
0x0
ADC_DCCTL3_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL3_CIC_LOW
Low Band
0x0
ADC_DCCTL3_CIC_MID
Mid Band
0x1
ADC_DCCTL3_CIC_HIGH
High Band
0x3
ADC_DCCTL3_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL3_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL3_CIM_ALWAYS
Always
0x0
ADC_DCCTL3_CIM_ONCE
Once
0x1
ADC_DCCTL3_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL3_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL3_CTC_LOW
Low Band
0x0
ADC_DCCTL3_CTC_MID
Mid Band
0x1
ADC_DCCTL3_CTC_HIGH
High Band
0x3
ADC_DCCTL3_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL3_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL3_CTM_ALWAYS
Always
0x0
ADC_DCCTL3_CTM_ONCE
Once
0x1
ADC_DCCTL3_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL4
ADC Digital Comparator Control 4
0xE10
read-write
n
0x0
0x0
ADC_DCCTL4_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL4_CIC_LOW
Low Band
0x0
ADC_DCCTL4_CIC_MID
Mid Band
0x1
ADC_DCCTL4_CIC_HIGH
High Band
0x3
ADC_DCCTL4_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL4_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL4_CIM_ALWAYS
Always
0x0
ADC_DCCTL4_CIM_ONCE
Once
0x1
ADC_DCCTL4_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL4_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL4_CTC_LOW
Low Band
0x0
ADC_DCCTL4_CTC_MID
Mid Band
0x1
ADC_DCCTL4_CTC_HIGH
High Band
0x3
ADC_DCCTL4_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL4_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL4_CTM_ALWAYS
Always
0x0
ADC_DCCTL4_CTM_ONCE
Once
0x1
ADC_DCCTL4_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL5
ADC Digital Comparator Control 5
0xE14
read-write
n
0x0
0x0
ADC_DCCTL5_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL5_CIC_LOW
Low Band
0x0
ADC_DCCTL5_CIC_MID
Mid Band
0x1
ADC_DCCTL5_CIC_HIGH
High Band
0x3
ADC_DCCTL5_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL5_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL5_CIM_ALWAYS
Always
0x0
ADC_DCCTL5_CIM_ONCE
Once
0x1
ADC_DCCTL5_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL5_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL5_CTC_LOW
Low Band
0x0
ADC_DCCTL5_CTC_MID
Mid Band
0x1
ADC_DCCTL5_CTC_HIGH
High Band
0x3
ADC_DCCTL5_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL5_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL5_CTM_ALWAYS
Always
0x0
ADC_DCCTL5_CTM_ONCE
Once
0x1
ADC_DCCTL5_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL6
ADC Digital Comparator Control 6
0xE18
read-write
n
0x0
0x0
ADC_DCCTL6_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL6_CIC_LOW
Low Band
0x0
ADC_DCCTL6_CIC_MID
Mid Band
0x1
ADC_DCCTL6_CIC_HIGH
High Band
0x3
ADC_DCCTL6_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL6_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL6_CIM_ALWAYS
Always
0x0
ADC_DCCTL6_CIM_ONCE
Once
0x1
ADC_DCCTL6_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL6_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL6_CTC_LOW
Low Band
0x0
ADC_DCCTL6_CTC_MID
Mid Band
0x1
ADC_DCCTL6_CTC_HIGH
High Band
0x3
ADC_DCCTL6_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL6_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL6_CTM_ALWAYS
Always
0x0
ADC_DCCTL6_CTM_ONCE
Once
0x1
ADC_DCCTL6_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL7
ADC Digital Comparator Control 7
0xE1C
read-write
n
0x0
0x0
ADC_DCCTL7_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL7_CIC_LOW
Low Band
0x0
ADC_DCCTL7_CIC_MID
Mid Band
0x1
ADC_DCCTL7_CIC_HIGH
High Band
0x3
ADC_DCCTL7_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL7_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL7_CIM_ALWAYS
Always
0x0
ADC_DCCTL7_CIM_ONCE
Once
0x1
ADC_DCCTL7_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL7_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL7_CTC_LOW
Low Band
0x0
ADC_DCCTL7_CTC_MID
Mid Band
0x1
ADC_DCCTL7_CTC_HIGH
High Band
0x3
ADC_DCCTL7_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL7_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL7_CTM_ALWAYS
Always
0x0
ADC_DCCTL7_CTM_ONCE
Once
0x1
ADC_DCCTL7_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CTM_HONCE
Hysteresis Once
0x3
ADC0DCISC
ADC Digital Comparator Interrupt Status and Clear
0x34
read-write
n
0x0
0x0
ADC_DCISC_DCINT0
Digital Comparator 0 Interrupt Status and Clear
0
1
ADC_DCISC_DCINT1
Digital Comparator 1 Interrupt Status and Clear
1
2
ADC_DCISC_DCINT2
Digital Comparator 2 Interrupt Status and Clear
2
3
ADC_DCISC_DCINT3
Digital Comparator 3 Interrupt Status and Clear
3
4
ADC_DCISC_DCINT4
Digital Comparator 4 Interrupt Status and Clear
4
5
ADC_DCISC_DCINT5
Digital Comparator 5 Interrupt Status and Clear
5
6
ADC_DCISC_DCINT6
Digital Comparator 6 Interrupt Status and Clear
6
7
ADC_DCISC_DCINT7
Digital Comparator 7 Interrupt Status and Clear
7
8
ADC0DCRIC
ADC Digital Comparator Reset Initial Conditions
0xD00
read-write
n
0x0
0x0
ADC_DCRIC_DCINT0
Digital Comparator Interrupt 0
0
1
ADC_DCRIC_DCINT1
Digital Comparator Interrupt 1
1
2
ADC_DCRIC_DCINT2
Digital Comparator Interrupt 2
2
3
ADC_DCRIC_DCINT3
Digital Comparator Interrupt 3
3
4
ADC_DCRIC_DCINT4
Digital Comparator Interrupt 4
4
5
ADC_DCRIC_DCINT5
Digital Comparator Interrupt 5
5
6
ADC_DCRIC_DCINT6
Digital Comparator Interrupt 6
6
7
ADC_DCRIC_DCINT7
Digital Comparator Interrupt 7
7
8
ADC_DCRIC_DCTRIG0
Digital Comparator Trigger 0
16
17
ADC_DCRIC_DCTRIG1
Digital Comparator Trigger 1
17
18
ADC_DCRIC_DCTRIG2
Digital Comparator Trigger 2
18
19
ADC_DCRIC_DCTRIG3
Digital Comparator Trigger 3
19
20
ADC_DCRIC_DCTRIG4
Digital Comparator Trigger 4
20
21
ADC_DCRIC_DCTRIG5
Digital Comparator Trigger 5
21
22
ADC_DCRIC_DCTRIG6
Digital Comparator Trigger 6
22
23
ADC_DCRIC_DCTRIG7
Digital Comparator Trigger 7
23
24
ADC0EMUX
ADC Event Multiplexer Select
0x14
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_PWM2
PWM2
0x8
ADC_EMUX_EM0_PWM3
PWM3
0x9
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_PWM2
PWM2
0x8
ADC_EMUX_EM1_PWM3
PWM3
0x9
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_PWM2
PWM2
0x8
ADC_EMUX_EM2_PWM3
PWM3
0x9
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_PWM2
PWM2
0x8
ADC_EMUX_EM3_PWM3
PWM3
0x9
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
ADC0IM
ADC Interrupt Mask
0x8
read-write
n
0x0
0x0
ADC_IM_DCONSS0
Digital Comparator Interrupt on SS0
16
17
ADC_IM_DCONSS1
Digital Comparator Interrupt on SS1
17
18
ADC_IM_DCONSS2
Digital Comparator Interrupt on SS2
18
19
ADC_IM_DCONSS3
Digital Comparator Interrupt on SS3
19
20
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ADC0ISC
ADC Interrupt Status and Clear
0xC
read-write
n
0x0
0x0
ADC_ISC_DCINSS0
Digital Comparator Interrupt Status on SS0
16
17
ADC_ISC_DCINSS1
Digital Comparator Interrupt Status on SS1
17
18
ADC_ISC_DCINSS2
Digital Comparator Interrupt Status on SS2
18
19
ADC_ISC_DCINSS3
Digital Comparator Interrupt Status on SS3
19
20
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
ADC0OSTAT
ADC Overflow Status
0x10
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
ADC0PSSI
ADC Processor Sample Sequence Initiate
0x28
read-write
n
0x0
0x0
ADC_PSSI_GSYNC
Global Synchronize
31
32
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
ADC_PSSI_SYNCWAIT
Synchronize Wait
27
28
ADC0RIS
ADC Raw Interrupt Status
0x4
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
ADC_RIS_INRDC
Digital Comparator Raw Interrupt Status
16
17
ADC0SAC
ADC Sample Averaging Control
0x30
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
ADC0SPC
ADC Sample Phase Control
0x24
read-write
n
0x0
0x0
ADC_SPC_PHASE
Phase Difference
0
4
ADC_SPC_PHASE_0
ADC sample lags by 0.0
0x0
ADC_SPC_PHASE_22_5
ADC sample lags by 22.5
0x1
ADC_SPC_PHASE_45
ADC sample lags by 45.0
0x2
ADC_SPC_PHASE_67_5
ADC sample lags by 67.5
0x3
ADC_SPC_PHASE_90
ADC sample lags by 90.0
0x4
ADC_SPC_PHASE_112_5
ADC sample lags by 112.5
0x5
ADC_SPC_PHASE_135
ADC sample lags by 135.0
0x6
ADC_SPC_PHASE_157_5
ADC sample lags by 157.5
0x7
ADC_SPC_PHASE_180
ADC sample lags by 180.0
0x8
ADC_SPC_PHASE_202_5
ADC sample lags by 202.5
0x9
ADC_SPC_PHASE_225
ADC sample lags by 225.0
0xa
ADC_SPC_PHASE_247_5
ADC sample lags by 247.5
0xb
ADC_SPC_PHASE_270
ADC sample lags by 270.0
0xc
ADC_SPC_PHASE_292_5
ADC sample lags by 292.5
0xd
ADC_SPC_PHASE_315
ADC sample lags by 315.0
0xe
ADC_SPC_PHASE_337_5
ADC sample lags by 337.5
0xf
ADC0SSCTL0
ADC Sample Sequence Control 0
0x44
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
ADC0SSCTL1
ADC Sample Sequence Control 1
0x64
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL2
ADC Sample Sequence Control 2
0x84
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL3
ADC Sample Sequence Control 3
0xA4
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
ADC0SSDC0
ADC Sample Sequence 0 Digital Comparator Select
0x54
read-write
n
0x0
0x0
ADC_SSDC0_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC0_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC0_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC0_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC_SSDC0_S4DCSEL
Sample 4 Digital Comparator Select
16
20
ADC_SSDC0_S5DCSEL
Sample 5 Digital Comparator Select
20
24
ADC_SSDC0_S6DCSEL
Sample 6 Digital Comparator Select
24
28
ADC_SSDC0_S7DCSEL
Sample 7 Digital Comparator Select
28
32
ADC0SSDC1
ADC Sample Sequence 1 Digital Comparator Select
0x74
read-write
n
0x0
0x0
ADC_SSDC1_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC1_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC1_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC1_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC0SSDC2
ADC Sample Sequence 2 Digital Comparator Select
0x94
read-write
n
0x0
0x0
ADC_SSDC2_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC2_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC2_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC2_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC0SSDC3
ADC Sample Sequence 3 Digital Comparator Select
0xB4
read-write
n
0x0
0x0
ADC_SSDC3_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC0SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
ADC0SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
ADC0SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
ADC0SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
ADC0SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
ADC0SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
4
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX0_MUX3
4th Sample Input Select
12
16
ADC_SSMUX0_MUX4
5th Sample Input Select
16
20
ADC_SSMUX0_MUX5
6th Sample Input Select
20
24
ADC_SSMUX0_MUX6
7th Sample Input Select
24
28
ADC_SSMUX0_MUX7
8th Sample Input Select
28
32
ADC0SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
4
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX1_MUX3
4th Sample Input Select
12
16
ADC0SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
4
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX2_MUX3
4th Sample Input Select
12
16
ADC0SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
4
ADC0SSOP0
ADC Sample Sequence 0 Operation
0x50
read-write
n
0x0
0x0
ADC_SSOP0_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP0_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP0_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP0_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC_SSOP0_S4DCOP
Sample 4 Digital Comparator Operation
16
17
ADC_SSOP0_S5DCOP
Sample 5 Digital Comparator Operation
20
21
ADC_SSOP0_S6DCOP
Sample 6 Digital Comparator Operation
24
25
ADC_SSOP0_S7DCOP
Sample 7 Digital Comparator Operation
28
29
ADC0SSOP1
ADC Sample Sequence 1 Operation
0x70
read-write
n
0x0
0x0
ADC_SSOP1_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP1_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP1_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP1_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC0SSOP2
ADC Sample Sequence 2 Operation
0x90
read-write
n
0x0
0x0
ADC_SSOP2_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP2_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP2_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP2_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC0SSOP3
ADC Sample Sequence 3 Operation
0xB0
read-write
n
0x0
0x0
ADC_SSOP3_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC0SSPRI
ADC Sample Sequencer Priority
0x20
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
ADC0USTAT
ADC Underflow Status
0x18
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
CTL
ADC Control
0x38
-1
read-write
n
0x0
0x0
ADC_CTL_VREF
Voltage Reference Select
0
1
DCCMP0
ADC Digital Comparator Range 0
0xE40
-1
read-write
n
0x0
0x0
ADC_DCCMP0_COMP0
Compare 0
0
10
ADC_DCCMP0_COMP1
Compare 1
16
26
DCCMP1
ADC Digital Comparator Range 1
0xE44
-1
read-write
n
0x0
0x0
ADC_DCCMP1_COMP0
Compare 0
0
10
ADC_DCCMP1_COMP1
Compare 1
16
26
DCCMP2
ADC Digital Comparator Range 2
0xE48
-1
read-write
n
0x0
0x0
ADC_DCCMP2_COMP0
Compare 0
0
10
ADC_DCCMP2_COMP1
Compare 1
16
26
DCCMP3
ADC Digital Comparator Range 3
0xE4C
-1
read-write
n
0x0
0x0
ADC_DCCMP3_COMP0
Compare 0
0
10
ADC_DCCMP3_COMP1
Compare 1
16
26
DCCMP4
ADC Digital Comparator Range 4
0xE50
-1
read-write
n
0x0
0x0
ADC_DCCMP4_COMP0
Compare 0
0
10
ADC_DCCMP4_COMP1
Compare 1
16
26
DCCMP5
ADC Digital Comparator Range 5
0xE54
-1
read-write
n
0x0
0x0
ADC_DCCMP5_COMP0
Compare 0
0
10
ADC_DCCMP5_COMP1
Compare 1
16
26
DCCMP6
ADC Digital Comparator Range 6
0xE58
-1
read-write
n
0x0
0x0
ADC_DCCMP6_COMP0
Compare 0
0
10
ADC_DCCMP6_COMP1
Compare 1
16
26
DCCMP7
ADC Digital Comparator Range 7
0xE5C
-1
read-write
n
0x0
0x0
ADC_DCCMP7_COMP0
Compare 0
0
10
ADC_DCCMP7_COMP1
Compare 1
16
26
DCCTL0
ADC Digital Comparator Control 0
0xE00
-1
read-write
n
0x0
0x0
ADC_DCCTL0_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL0_CIC_LOW
Low Band
0x0
ADC_DCCTL0_CIC_MID
Mid Band
0x1
ADC_DCCTL0_CIC_HIGH
High Band
0x3
ADC_DCCTL0_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL0_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL0_CIM_ALWAYS
Always
0x0
ADC_DCCTL0_CIM_ONCE
Once
0x1
ADC_DCCTL0_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL0_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL0_CTC_LOW
Low Band
0x0
ADC_DCCTL0_CTC_MID
Mid Band
0x1
ADC_DCCTL0_CTC_HIGH
High Band
0x3
ADC_DCCTL0_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL0_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL0_CTM_ALWAYS
Always
0x0
ADC_DCCTL0_CTM_ONCE
Once
0x1
ADC_DCCTL0_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CTM_HONCE
Hysteresis Once
0x3
DCCTL1
ADC Digital Comparator Control 1
0xE04
-1
read-write
n
0x0
0x0
ADC_DCCTL1_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL1_CIC_LOW
Low Band
0x0
ADC_DCCTL1_CIC_MID
Mid Band
0x1
ADC_DCCTL1_CIC_HIGH
High Band
0x3
ADC_DCCTL1_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL1_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL1_CIM_ALWAYS
Always
0x0
ADC_DCCTL1_CIM_ONCE
Once
0x1
ADC_DCCTL1_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL1_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL1_CTC_LOW
Low Band
0x0
ADC_DCCTL1_CTC_MID
Mid Band
0x1
ADC_DCCTL1_CTC_HIGH
High Band
0x3
ADC_DCCTL1_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL1_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL1_CTM_ALWAYS
Always
0x0
ADC_DCCTL1_CTM_ONCE
Once
0x1
ADC_DCCTL1_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CTM_HONCE
Hysteresis Once
0x3
DCCTL2
ADC Digital Comparator Control 2
0xE08
-1
read-write
n
0x0
0x0
ADC_DCCTL2_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL2_CIC_LOW
Low Band
0x0
ADC_DCCTL2_CIC_MID
Mid Band
0x1
ADC_DCCTL2_CIC_HIGH
High Band
0x3
ADC_DCCTL2_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL2_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL2_CIM_ALWAYS
Always
0x0
ADC_DCCTL2_CIM_ONCE
Once
0x1
ADC_DCCTL2_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL2_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL2_CTC_LOW
Low Band
0x0
ADC_DCCTL2_CTC_MID
Mid Band
0x1
ADC_DCCTL2_CTC_HIGH
High Band
0x3
ADC_DCCTL2_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL2_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL2_CTM_ALWAYS
Always
0x0
ADC_DCCTL2_CTM_ONCE
Once
0x1
ADC_DCCTL2_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CTM_HONCE
Hysteresis Once
0x3
DCCTL3
ADC Digital Comparator Control 3
0xE0C
-1
read-write
n
0x0
0x0
ADC_DCCTL3_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL3_CIC_LOW
Low Band
0x0
ADC_DCCTL3_CIC_MID
Mid Band
0x1
ADC_DCCTL3_CIC_HIGH
High Band
0x3
ADC_DCCTL3_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL3_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL3_CIM_ALWAYS
Always
0x0
ADC_DCCTL3_CIM_ONCE
Once
0x1
ADC_DCCTL3_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL3_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL3_CTC_LOW
Low Band
0x0
ADC_DCCTL3_CTC_MID
Mid Band
0x1
ADC_DCCTL3_CTC_HIGH
High Band
0x3
ADC_DCCTL3_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL3_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL3_CTM_ALWAYS
Always
0x0
ADC_DCCTL3_CTM_ONCE
Once
0x1
ADC_DCCTL3_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CTM_HONCE
Hysteresis Once
0x3
DCCTL4
ADC Digital Comparator Control 4
0xE10
-1
read-write
n
0x0
0x0
ADC_DCCTL4_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL4_CIC_LOW
Low Band
0x0
ADC_DCCTL4_CIC_MID
Mid Band
0x1
ADC_DCCTL4_CIC_HIGH
High Band
0x3
ADC_DCCTL4_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL4_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL4_CIM_ALWAYS
Always
0x0
ADC_DCCTL4_CIM_ONCE
Once
0x1
ADC_DCCTL4_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL4_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL4_CTC_LOW
Low Band
0x0
ADC_DCCTL4_CTC_MID
Mid Band
0x1
ADC_DCCTL4_CTC_HIGH
High Band
0x3
ADC_DCCTL4_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL4_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL4_CTM_ALWAYS
Always
0x0
ADC_DCCTL4_CTM_ONCE
Once
0x1
ADC_DCCTL4_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CTM_HONCE
Hysteresis Once
0x3
DCCTL5
ADC Digital Comparator Control 5
0xE14
-1
read-write
n
0x0
0x0
ADC_DCCTL5_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL5_CIC_LOW
Low Band
0x0
ADC_DCCTL5_CIC_MID
Mid Band
0x1
ADC_DCCTL5_CIC_HIGH
High Band
0x3
ADC_DCCTL5_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL5_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL5_CIM_ALWAYS
Always
0x0
ADC_DCCTL5_CIM_ONCE
Once
0x1
ADC_DCCTL5_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL5_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL5_CTC_LOW
Low Band
0x0
ADC_DCCTL5_CTC_MID
Mid Band
0x1
ADC_DCCTL5_CTC_HIGH
High Band
0x3
ADC_DCCTL5_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL5_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL5_CTM_ALWAYS
Always
0x0
ADC_DCCTL5_CTM_ONCE
Once
0x1
ADC_DCCTL5_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CTM_HONCE
Hysteresis Once
0x3
DCCTL6
ADC Digital Comparator Control 6
0xE18
-1
read-write
n
0x0
0x0
ADC_DCCTL6_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL6_CIC_LOW
Low Band
0x0
ADC_DCCTL6_CIC_MID
Mid Band
0x1
ADC_DCCTL6_CIC_HIGH
High Band
0x3
ADC_DCCTL6_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL6_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL6_CIM_ALWAYS
Always
0x0
ADC_DCCTL6_CIM_ONCE
Once
0x1
ADC_DCCTL6_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL6_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL6_CTC_LOW
Low Band
0x0
ADC_DCCTL6_CTC_MID
Mid Band
0x1
ADC_DCCTL6_CTC_HIGH
High Band
0x3
ADC_DCCTL6_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL6_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL6_CTM_ALWAYS
Always
0x0
ADC_DCCTL6_CTM_ONCE
Once
0x1
ADC_DCCTL6_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CTM_HONCE
Hysteresis Once
0x3
DCCTL7
ADC Digital Comparator Control 7
0xE1C
-1
read-write
n
0x0
0x0
ADC_DCCTL7_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL7_CIC_LOW
Low Band
0x0
ADC_DCCTL7_CIC_MID
Mid Band
0x1
ADC_DCCTL7_CIC_HIGH
High Band
0x3
ADC_DCCTL7_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL7_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL7_CIM_ALWAYS
Always
0x0
ADC_DCCTL7_CIM_ONCE
Once
0x1
ADC_DCCTL7_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL7_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL7_CTC_LOW
Low Band
0x0
ADC_DCCTL7_CTC_MID
Mid Band
0x1
ADC_DCCTL7_CTC_HIGH
High Band
0x3
ADC_DCCTL7_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL7_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL7_CTM_ALWAYS
Always
0x0
ADC_DCCTL7_CTM_ONCE
Once
0x1
ADC_DCCTL7_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CTM_HONCE
Hysteresis Once
0x3
DCISC
ADC Digital Comparator Interrupt Status and Clear
0x34
-1
read-write
n
0x0
0x0
ADC_DCISC_DCINT0
Digital Comparator 0 Interrupt Status and Clear
0
1
ADC_DCISC_DCINT1
Digital Comparator 1 Interrupt Status and Clear
1
2
ADC_DCISC_DCINT2
Digital Comparator 2 Interrupt Status and Clear
2
3
ADC_DCISC_DCINT3
Digital Comparator 3 Interrupt Status and Clear
3
4
ADC_DCISC_DCINT4
Digital Comparator 4 Interrupt Status and Clear
4
5
ADC_DCISC_DCINT5
Digital Comparator 5 Interrupt Status and Clear
5
6
ADC_DCISC_DCINT6
Digital Comparator 6 Interrupt Status and Clear
6
7
ADC_DCISC_DCINT7
Digital Comparator 7 Interrupt Status and Clear
7
8
DCRIC
ADC Digital Comparator Reset Initial Conditions
0xD00
-1
read-write
n
0x0
0x0
ADC_DCRIC_DCINT0
Digital Comparator Interrupt 0
0
1
ADC_DCRIC_DCINT1
Digital Comparator Interrupt 1
1
2
ADC_DCRIC_DCINT2
Digital Comparator Interrupt 2
2
3
ADC_DCRIC_DCINT3
Digital Comparator Interrupt 3
3
4
ADC_DCRIC_DCINT4
Digital Comparator Interrupt 4
4
5
ADC_DCRIC_DCINT5
Digital Comparator Interrupt 5
5
6
ADC_DCRIC_DCINT6
Digital Comparator Interrupt 6
6
7
ADC_DCRIC_DCINT7
Digital Comparator Interrupt 7
7
8
ADC_DCRIC_DCTRIG0
Digital Comparator Trigger 0
16
17
ADC_DCRIC_DCTRIG1
Digital Comparator Trigger 1
17
18
ADC_DCRIC_DCTRIG2
Digital Comparator Trigger 2
18
19
ADC_DCRIC_DCTRIG3
Digital Comparator Trigger 3
19
20
ADC_DCRIC_DCTRIG4
Digital Comparator Trigger 4
20
21
ADC_DCRIC_DCTRIG5
Digital Comparator Trigger 5
21
22
ADC_DCRIC_DCTRIG6
Digital Comparator Trigger 6
22
23
ADC_DCRIC_DCTRIG7
Digital Comparator Trigger 7
23
24
EMUX
ADC Event Multiplexer Select
0x14
-1
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_PWM2
PWM2
0x8
ADC_EMUX_EM0_PWM3
PWM3
0x9
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_PWM2
PWM2
0x8
ADC_EMUX_EM1_PWM3
PWM3
0x9
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_PWM2
PWM2
0x8
ADC_EMUX_EM2_PWM3
PWM3
0x9
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_PWM2
PWM2
0x8
ADC_EMUX_EM3_PWM3
PWM3
0x9
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
IM
ADC Interrupt Mask
0x8
-1
read-write
n
0x0
0x0
ADC_IM_DCONSS0
Digital Comparator Interrupt on SS0
16
17
ADC_IM_DCONSS1
Digital Comparator Interrupt on SS1
17
18
ADC_IM_DCONSS2
Digital Comparator Interrupt on SS2
18
19
ADC_IM_DCONSS3
Digital Comparator Interrupt on SS3
19
20
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ISC
ADC Interrupt Status and Clear
0xC
-1
read-write
n
0x0
0x0
ADC_ISC_DCINSS0
Digital Comparator Interrupt Status on SS0
16
17
ADC_ISC_DCINSS1
Digital Comparator Interrupt Status on SS1
17
18
ADC_ISC_DCINSS2
Digital Comparator Interrupt Status on SS2
18
19
ADC_ISC_DCINSS3
Digital Comparator Interrupt Status on SS3
19
20
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
OSTAT
ADC Overflow Status
0x10
-1
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
PSSI
ADC Processor Sample Sequence Initiate
0x28
-1
read-write
n
0x0
0x0
ADC_PSSI_GSYNC
Global Synchronize
31
32
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
ADC_PSSI_SYNCWAIT
Synchronize Wait
27
28
RIS
ADC Raw Interrupt Status
0x4
-1
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
ADC_RIS_INRDC
Digital Comparator Raw Interrupt Status
16
17
SAC
ADC Sample Averaging Control
0x30
-1
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
SPC
ADC Sample Phase Control
0x24
-1
read-write
n
0x0
0x0
ADC_SPC_PHASE
Phase Difference
0
4
ADC_SPC_PHASE_0
ADC sample lags by 0.0
0x0
ADC_SPC_PHASE_22_5
ADC sample lags by 22.5
0x1
ADC_SPC_PHASE_45
ADC sample lags by 45.0
0x2
ADC_SPC_PHASE_67_5
ADC sample lags by 67.5
0x3
ADC_SPC_PHASE_90
ADC sample lags by 90.0
0x4
ADC_SPC_PHASE_112_5
ADC sample lags by 112.5
0x5
ADC_SPC_PHASE_135
ADC sample lags by 135.0
0x6
ADC_SPC_PHASE_157_5
ADC sample lags by 157.5
0x7
ADC_SPC_PHASE_180
ADC sample lags by 180.0
0x8
ADC_SPC_PHASE_202_5
ADC sample lags by 202.5
0x9
ADC_SPC_PHASE_225
ADC sample lags by 225.0
0xa
ADC_SPC_PHASE_247_5
ADC sample lags by 247.5
0xb
ADC_SPC_PHASE_270
ADC sample lags by 270.0
0xc
ADC_SPC_PHASE_292_5
ADC sample lags by 292.5
0xd
ADC_SPC_PHASE_315
ADC sample lags by 315.0
0xe
ADC_SPC_PHASE_337_5
ADC sample lags by 337.5
0xf
SSCTL0
ADC Sample Sequence Control 0
0x44
-1
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
SSCTL1
ADC Sample Sequence Control 1
0x64
-1
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
SSCTL2
ADC Sample Sequence Control 2
0x84
-1
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
SSCTL3
ADC Sample Sequence Control 3
0xA4
-1
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
SSDC0
ADC Sample Sequence 0 Digital Comparator Select
0x54
-1
read-write
n
0x0
0x0
ADC_SSDC0_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC0_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC0_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC0_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC_SSDC0_S4DCSEL
Sample 4 Digital Comparator Select
16
20
ADC_SSDC0_S5DCSEL
Sample 5 Digital Comparator Select
20
24
ADC_SSDC0_S6DCSEL
Sample 6 Digital Comparator Select
24
28
ADC_SSDC0_S7DCSEL
Sample 7 Digital Comparator Select
28
32
SSDC1
ADC Sample Sequence 1 Digital Comparator Select
0x74
-1
read-write
n
0x0
0x0
ADC_SSDC1_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC1_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC1_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC1_S3DCSEL
Sample 3 Digital Comparator Select
12
16
SSDC2
ADC Sample Sequence 2 Digital Comparator Select
0x94
-1
read-write
n
0x0
0x0
ADC_SSDC2_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC2_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC2_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC2_S3DCSEL
Sample 3 Digital Comparator Select
12
16
SSDC3
ADC Sample Sequence 3 Digital Comparator Select
0xB4
-1
read-write
n
0x0
0x0
ADC_SSDC3_S0DCSEL
Sample 0 Digital Comparator Select
0
4
SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
-1
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
-1
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
-1
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
-1
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
-1
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
-1
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
4
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX0_MUX3
4th Sample Input Select
12
16
ADC_SSMUX0_MUX4
5th Sample Input Select
16
20
ADC_SSMUX0_MUX5
6th Sample Input Select
20
24
ADC_SSMUX0_MUX6
7th Sample Input Select
24
28
ADC_SSMUX0_MUX7
8th Sample Input Select
28
32
SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
-1
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
4
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX1_MUX3
4th Sample Input Select
12
16
SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
-1
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
4
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX2_MUX3
4th Sample Input Select
12
16
SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
-1
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
4
SSOP0
ADC Sample Sequence 0 Operation
0x50
-1
read-write
n
0x0
0x0
ADC_SSOP0_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP0_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP0_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP0_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC_SSOP0_S4DCOP
Sample 4 Digital Comparator Operation
16
17
ADC_SSOP0_S5DCOP
Sample 5 Digital Comparator Operation
20
21
ADC_SSOP0_S6DCOP
Sample 6 Digital Comparator Operation
24
25
ADC_SSOP0_S7DCOP
Sample 7 Digital Comparator Operation
28
29
SSOP1
ADC Sample Sequence 1 Operation
0x70
-1
read-write
n
0x0
0x0
ADC_SSOP1_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP1_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP1_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP1_S3DCOP
Sample 3 Digital Comparator Operation
12
13
SSOP2
ADC Sample Sequence 2 Operation
0x90
-1
read-write
n
0x0
0x0
ADC_SSOP2_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP2_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP2_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP2_S3DCOP
Sample 3 Digital Comparator Operation
12
13
SSOP3
ADC Sample Sequence 3 Operation
0xB0
-1
read-write
n
0x0
0x0
ADC_SSOP3_S0DCOP
Sample 0 Digital Comparator Operation
0
1
SSPRI
ADC Sample Sequencer Priority
0x20
-1
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
USTAT
ADC Underflow Status
0x18
-1
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
ADC1
Register map for ADC0 peripheral
ADC
0x0
0x0
0x1000
registers
n
ACTSS
ADC Active Sample Sequencer
0x0
-1
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0ACTSS
ADC Active Sample Sequencer
0x0
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0CTL
ADC Control
0x38
read-write
n
0x0
0x0
ADC_CTL_VREF
Voltage Reference Select
0
1
ADC0DCCMP0
ADC Digital Comparator Range 0
0xE40
read-write
n
0x0
0x0
ADC_DCCMP0_COMP0
Compare 0
0
10
ADC_DCCMP0_COMP1
Compare 1
16
26
ADC0DCCMP1
ADC Digital Comparator Range 1
0xE44
read-write
n
0x0
0x0
ADC_DCCMP1_COMP0
Compare 0
0
10
ADC_DCCMP1_COMP1
Compare 1
16
26
ADC0DCCMP2
ADC Digital Comparator Range 2
0xE48
read-write
n
0x0
0x0
ADC_DCCMP2_COMP0
Compare 0
0
10
ADC_DCCMP2_COMP1
Compare 1
16
26
ADC0DCCMP3
ADC Digital Comparator Range 3
0xE4C
read-write
n
0x0
0x0
ADC_DCCMP3_COMP0
Compare 0
0
10
ADC_DCCMP3_COMP1
Compare 1
16
26
ADC0DCCMP4
ADC Digital Comparator Range 4
0xE50
read-write
n
0x0
0x0
ADC_DCCMP4_COMP0
Compare 0
0
10
ADC_DCCMP4_COMP1
Compare 1
16
26
ADC0DCCMP5
ADC Digital Comparator Range 5
0xE54
read-write
n
0x0
0x0
ADC_DCCMP5_COMP0
Compare 0
0
10
ADC_DCCMP5_COMP1
Compare 1
16
26
ADC0DCCMP6
ADC Digital Comparator Range 6
0xE58
read-write
n
0x0
0x0
ADC_DCCMP6_COMP0
Compare 0
0
10
ADC_DCCMP6_COMP1
Compare 1
16
26
ADC0DCCMP7
ADC Digital Comparator Range 7
0xE5C
read-write
n
0x0
0x0
ADC_DCCMP7_COMP0
Compare 0
0
10
ADC_DCCMP7_COMP1
Compare 1
16
26
ADC0DCCTL0
ADC Digital Comparator Control 0
0xE00
read-write
n
0x0
0x0
ADC_DCCTL0_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL0_CIC_LOW
Low Band
0x0
ADC_DCCTL0_CIC_MID
Mid Band
0x1
ADC_DCCTL0_CIC_HIGH
High Band
0x3
ADC_DCCTL0_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL0_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL0_CIM_ALWAYS
Always
0x0
ADC_DCCTL0_CIM_ONCE
Once
0x1
ADC_DCCTL0_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL0_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL0_CTC_LOW
Low Band
0x0
ADC_DCCTL0_CTC_MID
Mid Band
0x1
ADC_DCCTL0_CTC_HIGH
High Band
0x3
ADC_DCCTL0_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL0_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL0_CTM_ALWAYS
Always
0x0
ADC_DCCTL0_CTM_ONCE
Once
0x1
ADC_DCCTL0_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL1
ADC Digital Comparator Control 1
0xE04
read-write
n
0x0
0x0
ADC_DCCTL1_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL1_CIC_LOW
Low Band
0x0
ADC_DCCTL1_CIC_MID
Mid Band
0x1
ADC_DCCTL1_CIC_HIGH
High Band
0x3
ADC_DCCTL1_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL1_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL1_CIM_ALWAYS
Always
0x0
ADC_DCCTL1_CIM_ONCE
Once
0x1
ADC_DCCTL1_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL1_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL1_CTC_LOW
Low Band
0x0
ADC_DCCTL1_CTC_MID
Mid Band
0x1
ADC_DCCTL1_CTC_HIGH
High Band
0x3
ADC_DCCTL1_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL1_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL1_CTM_ALWAYS
Always
0x0
ADC_DCCTL1_CTM_ONCE
Once
0x1
ADC_DCCTL1_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL2
ADC Digital Comparator Control 2
0xE08
read-write
n
0x0
0x0
ADC_DCCTL2_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL2_CIC_LOW
Low Band
0x0
ADC_DCCTL2_CIC_MID
Mid Band
0x1
ADC_DCCTL2_CIC_HIGH
High Band
0x3
ADC_DCCTL2_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL2_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL2_CIM_ALWAYS
Always
0x0
ADC_DCCTL2_CIM_ONCE
Once
0x1
ADC_DCCTL2_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL2_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL2_CTC_LOW
Low Band
0x0
ADC_DCCTL2_CTC_MID
Mid Band
0x1
ADC_DCCTL2_CTC_HIGH
High Band
0x3
ADC_DCCTL2_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL2_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL2_CTM_ALWAYS
Always
0x0
ADC_DCCTL2_CTM_ONCE
Once
0x1
ADC_DCCTL2_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL3
ADC Digital Comparator Control 3
0xE0C
read-write
n
0x0
0x0
ADC_DCCTL3_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL3_CIC_LOW
Low Band
0x0
ADC_DCCTL3_CIC_MID
Mid Band
0x1
ADC_DCCTL3_CIC_HIGH
High Band
0x3
ADC_DCCTL3_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL3_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL3_CIM_ALWAYS
Always
0x0
ADC_DCCTL3_CIM_ONCE
Once
0x1
ADC_DCCTL3_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL3_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL3_CTC_LOW
Low Band
0x0
ADC_DCCTL3_CTC_MID
Mid Band
0x1
ADC_DCCTL3_CTC_HIGH
High Band
0x3
ADC_DCCTL3_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL3_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL3_CTM_ALWAYS
Always
0x0
ADC_DCCTL3_CTM_ONCE
Once
0x1
ADC_DCCTL3_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL4
ADC Digital Comparator Control 4
0xE10
read-write
n
0x0
0x0
ADC_DCCTL4_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL4_CIC_LOW
Low Band
0x0
ADC_DCCTL4_CIC_MID
Mid Band
0x1
ADC_DCCTL4_CIC_HIGH
High Band
0x3
ADC_DCCTL4_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL4_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL4_CIM_ALWAYS
Always
0x0
ADC_DCCTL4_CIM_ONCE
Once
0x1
ADC_DCCTL4_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL4_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL4_CTC_LOW
Low Band
0x0
ADC_DCCTL4_CTC_MID
Mid Band
0x1
ADC_DCCTL4_CTC_HIGH
High Band
0x3
ADC_DCCTL4_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL4_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL4_CTM_ALWAYS
Always
0x0
ADC_DCCTL4_CTM_ONCE
Once
0x1
ADC_DCCTL4_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL5
ADC Digital Comparator Control 5
0xE14
read-write
n
0x0
0x0
ADC_DCCTL5_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL5_CIC_LOW
Low Band
0x0
ADC_DCCTL5_CIC_MID
Mid Band
0x1
ADC_DCCTL5_CIC_HIGH
High Band
0x3
ADC_DCCTL5_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL5_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL5_CIM_ALWAYS
Always
0x0
ADC_DCCTL5_CIM_ONCE
Once
0x1
ADC_DCCTL5_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL5_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL5_CTC_LOW
Low Band
0x0
ADC_DCCTL5_CTC_MID
Mid Band
0x1
ADC_DCCTL5_CTC_HIGH
High Band
0x3
ADC_DCCTL5_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL5_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL5_CTM_ALWAYS
Always
0x0
ADC_DCCTL5_CTM_ONCE
Once
0x1
ADC_DCCTL5_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL6
ADC Digital Comparator Control 6
0xE18
read-write
n
0x0
0x0
ADC_DCCTL6_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL6_CIC_LOW
Low Band
0x0
ADC_DCCTL6_CIC_MID
Mid Band
0x1
ADC_DCCTL6_CIC_HIGH
High Band
0x3
ADC_DCCTL6_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL6_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL6_CIM_ALWAYS
Always
0x0
ADC_DCCTL6_CIM_ONCE
Once
0x1
ADC_DCCTL6_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL6_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL6_CTC_LOW
Low Band
0x0
ADC_DCCTL6_CTC_MID
Mid Band
0x1
ADC_DCCTL6_CTC_HIGH
High Band
0x3
ADC_DCCTL6_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL6_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL6_CTM_ALWAYS
Always
0x0
ADC_DCCTL6_CTM_ONCE
Once
0x1
ADC_DCCTL6_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CTM_HONCE
Hysteresis Once
0x3
ADC0DCCTL7
ADC Digital Comparator Control 7
0xE1C
read-write
n
0x0
0x0
ADC_DCCTL7_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL7_CIC_LOW
Low Band
0x0
ADC_DCCTL7_CIC_MID
Mid Band
0x1
ADC_DCCTL7_CIC_HIGH
High Band
0x3
ADC_DCCTL7_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL7_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL7_CIM_ALWAYS
Always
0x0
ADC_DCCTL7_CIM_ONCE
Once
0x1
ADC_DCCTL7_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL7_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL7_CTC_LOW
Low Band
0x0
ADC_DCCTL7_CTC_MID
Mid Band
0x1
ADC_DCCTL7_CTC_HIGH
High Band
0x3
ADC_DCCTL7_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL7_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL7_CTM_ALWAYS
Always
0x0
ADC_DCCTL7_CTM_ONCE
Once
0x1
ADC_DCCTL7_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CTM_HONCE
Hysteresis Once
0x3
ADC0DCISC
ADC Digital Comparator Interrupt Status and Clear
0x34
read-write
n
0x0
0x0
ADC_DCISC_DCINT0
Digital Comparator 0 Interrupt Status and Clear
0
1
ADC_DCISC_DCINT1
Digital Comparator 1 Interrupt Status and Clear
1
2
ADC_DCISC_DCINT2
Digital Comparator 2 Interrupt Status and Clear
2
3
ADC_DCISC_DCINT3
Digital Comparator 3 Interrupt Status and Clear
3
4
ADC_DCISC_DCINT4
Digital Comparator 4 Interrupt Status and Clear
4
5
ADC_DCISC_DCINT5
Digital Comparator 5 Interrupt Status and Clear
5
6
ADC_DCISC_DCINT6
Digital Comparator 6 Interrupt Status and Clear
6
7
ADC_DCISC_DCINT7
Digital Comparator 7 Interrupt Status and Clear
7
8
ADC0DCRIC
ADC Digital Comparator Reset Initial Conditions
0xD00
read-write
n
0x0
0x0
ADC_DCRIC_DCINT0
Digital Comparator Interrupt 0
0
1
ADC_DCRIC_DCINT1
Digital Comparator Interrupt 1
1
2
ADC_DCRIC_DCINT2
Digital Comparator Interrupt 2
2
3
ADC_DCRIC_DCINT3
Digital Comparator Interrupt 3
3
4
ADC_DCRIC_DCINT4
Digital Comparator Interrupt 4
4
5
ADC_DCRIC_DCINT5
Digital Comparator Interrupt 5
5
6
ADC_DCRIC_DCINT6
Digital Comparator Interrupt 6
6
7
ADC_DCRIC_DCINT7
Digital Comparator Interrupt 7
7
8
ADC_DCRIC_DCTRIG0
Digital Comparator Trigger 0
16
17
ADC_DCRIC_DCTRIG1
Digital Comparator Trigger 1
17
18
ADC_DCRIC_DCTRIG2
Digital Comparator Trigger 2
18
19
ADC_DCRIC_DCTRIG3
Digital Comparator Trigger 3
19
20
ADC_DCRIC_DCTRIG4
Digital Comparator Trigger 4
20
21
ADC_DCRIC_DCTRIG5
Digital Comparator Trigger 5
21
22
ADC_DCRIC_DCTRIG6
Digital Comparator Trigger 6
22
23
ADC_DCRIC_DCTRIG7
Digital Comparator Trigger 7
23
24
ADC0EMUX
ADC Event Multiplexer Select
0x14
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_PWM2
PWM2
0x8
ADC_EMUX_EM0_PWM3
PWM3
0x9
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_PWM2
PWM2
0x8
ADC_EMUX_EM1_PWM3
PWM3
0x9
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_PWM2
PWM2
0x8
ADC_EMUX_EM2_PWM3
PWM3
0x9
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_PWM2
PWM2
0x8
ADC_EMUX_EM3_PWM3
PWM3
0x9
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
ADC0IM
ADC Interrupt Mask
0x8
read-write
n
0x0
0x0
ADC_IM_DCONSS0
Digital Comparator Interrupt on SS0
16
17
ADC_IM_DCONSS1
Digital Comparator Interrupt on SS1
17
18
ADC_IM_DCONSS2
Digital Comparator Interrupt on SS2
18
19
ADC_IM_DCONSS3
Digital Comparator Interrupt on SS3
19
20
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ADC0ISC
ADC Interrupt Status and Clear
0xC
read-write
n
0x0
0x0
ADC_ISC_DCINSS0
Digital Comparator Interrupt Status on SS0
16
17
ADC_ISC_DCINSS1
Digital Comparator Interrupt Status on SS1
17
18
ADC_ISC_DCINSS2
Digital Comparator Interrupt Status on SS2
18
19
ADC_ISC_DCINSS3
Digital Comparator Interrupt Status on SS3
19
20
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
ADC0OSTAT
ADC Overflow Status
0x10
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
ADC0PSSI
ADC Processor Sample Sequence Initiate
0x28
read-write
n
0x0
0x0
ADC_PSSI_GSYNC
Global Synchronize
31
32
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
ADC_PSSI_SYNCWAIT
Synchronize Wait
27
28
ADC0RIS
ADC Raw Interrupt Status
0x4
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
ADC_RIS_INRDC
Digital Comparator Raw Interrupt Status
16
17
ADC0SAC
ADC Sample Averaging Control
0x30
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
ADC0SPC
ADC Sample Phase Control
0x24
read-write
n
0x0
0x0
ADC_SPC_PHASE
Phase Difference
0
4
ADC_SPC_PHASE_0
ADC sample lags by 0.0
0x0
ADC_SPC_PHASE_22_5
ADC sample lags by 22.5
0x1
ADC_SPC_PHASE_45
ADC sample lags by 45.0
0x2
ADC_SPC_PHASE_67_5
ADC sample lags by 67.5
0x3
ADC_SPC_PHASE_90
ADC sample lags by 90.0
0x4
ADC_SPC_PHASE_112_5
ADC sample lags by 112.5
0x5
ADC_SPC_PHASE_135
ADC sample lags by 135.0
0x6
ADC_SPC_PHASE_157_5
ADC sample lags by 157.5
0x7
ADC_SPC_PHASE_180
ADC sample lags by 180.0
0x8
ADC_SPC_PHASE_202_5
ADC sample lags by 202.5
0x9
ADC_SPC_PHASE_225
ADC sample lags by 225.0
0xa
ADC_SPC_PHASE_247_5
ADC sample lags by 247.5
0xb
ADC_SPC_PHASE_270
ADC sample lags by 270.0
0xc
ADC_SPC_PHASE_292_5
ADC sample lags by 292.5
0xd
ADC_SPC_PHASE_315
ADC sample lags by 315.0
0xe
ADC_SPC_PHASE_337_5
ADC sample lags by 337.5
0xf
ADC0SSCTL0
ADC Sample Sequence Control 0
0x44
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
ADC0SSCTL1
ADC Sample Sequence Control 1
0x64
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL2
ADC Sample Sequence Control 2
0x84
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL3
ADC Sample Sequence Control 3
0xA4
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
ADC0SSDC0
ADC Sample Sequence 0 Digital Comparator Select
0x54
read-write
n
0x0
0x0
ADC_SSDC0_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC0_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC0_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC0_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC_SSDC0_S4DCSEL
Sample 4 Digital Comparator Select
16
20
ADC_SSDC0_S5DCSEL
Sample 5 Digital Comparator Select
20
24
ADC_SSDC0_S6DCSEL
Sample 6 Digital Comparator Select
24
28
ADC_SSDC0_S7DCSEL
Sample 7 Digital Comparator Select
28
32
ADC0SSDC1
ADC Sample Sequence 1 Digital Comparator Select
0x74
read-write
n
0x0
0x0
ADC_SSDC1_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC1_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC1_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC1_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC0SSDC2
ADC Sample Sequence 2 Digital Comparator Select
0x94
read-write
n
0x0
0x0
ADC_SSDC2_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC2_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC2_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC2_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC0SSDC3
ADC Sample Sequence 3 Digital Comparator Select
0xB4
read-write
n
0x0
0x0
ADC_SSDC3_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC0SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
ADC0SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
ADC0SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
ADC0SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
ADC0SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
ADC0SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
4
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX0_MUX3
4th Sample Input Select
12
16
ADC_SSMUX0_MUX4
5th Sample Input Select
16
20
ADC_SSMUX0_MUX5
6th Sample Input Select
20
24
ADC_SSMUX0_MUX6
7th Sample Input Select
24
28
ADC_SSMUX0_MUX7
8th Sample Input Select
28
32
ADC0SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
4
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX1_MUX3
4th Sample Input Select
12
16
ADC0SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
4
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX2_MUX3
4th Sample Input Select
12
16
ADC0SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
4
ADC0SSOP0
ADC Sample Sequence 0 Operation
0x50
read-write
n
0x0
0x0
ADC_SSOP0_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP0_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP0_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP0_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC_SSOP0_S4DCOP
Sample 4 Digital Comparator Operation
16
17
ADC_SSOP0_S5DCOP
Sample 5 Digital Comparator Operation
20
21
ADC_SSOP0_S6DCOP
Sample 6 Digital Comparator Operation
24
25
ADC_SSOP0_S7DCOP
Sample 7 Digital Comparator Operation
28
29
ADC0SSOP1
ADC Sample Sequence 1 Operation
0x70
read-write
n
0x0
0x0
ADC_SSOP1_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP1_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP1_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP1_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC0SSOP2
ADC Sample Sequence 2 Operation
0x90
read-write
n
0x0
0x0
ADC_SSOP2_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP2_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP2_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP2_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC0SSOP3
ADC Sample Sequence 3 Operation
0xB0
read-write
n
0x0
0x0
ADC_SSOP3_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC0SSPRI
ADC Sample Sequencer Priority
0x20
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
ADC0USTAT
ADC Underflow Status
0x18
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
CTL
ADC Control
0x38
-1
read-write
n
0x0
0x0
ADC_CTL_VREF
Voltage Reference Select
0
1
DCCMP0
ADC Digital Comparator Range 0
0xE40
-1
read-write
n
0x0
0x0
ADC_DCCMP0_COMP0
Compare 0
0
10
ADC_DCCMP0_COMP1
Compare 1
16
26
DCCMP1
ADC Digital Comparator Range 1
0xE44
-1
read-write
n
0x0
0x0
ADC_DCCMP1_COMP0
Compare 0
0
10
ADC_DCCMP1_COMP1
Compare 1
16
26
DCCMP2
ADC Digital Comparator Range 2
0xE48
-1
read-write
n
0x0
0x0
ADC_DCCMP2_COMP0
Compare 0
0
10
ADC_DCCMP2_COMP1
Compare 1
16
26
DCCMP3
ADC Digital Comparator Range 3
0xE4C
-1
read-write
n
0x0
0x0
ADC_DCCMP3_COMP0
Compare 0
0
10
ADC_DCCMP3_COMP1
Compare 1
16
26
DCCMP4
ADC Digital Comparator Range 4
0xE50
-1
read-write
n
0x0
0x0
ADC_DCCMP4_COMP0
Compare 0
0
10
ADC_DCCMP4_COMP1
Compare 1
16
26
DCCMP5
ADC Digital Comparator Range 5
0xE54
-1
read-write
n
0x0
0x0
ADC_DCCMP5_COMP0
Compare 0
0
10
ADC_DCCMP5_COMP1
Compare 1
16
26
DCCMP6
ADC Digital Comparator Range 6
0xE58
-1
read-write
n
0x0
0x0
ADC_DCCMP6_COMP0
Compare 0
0
10
ADC_DCCMP6_COMP1
Compare 1
16
26
DCCMP7
ADC Digital Comparator Range 7
0xE5C
-1
read-write
n
0x0
0x0
ADC_DCCMP7_COMP0
Compare 0
0
10
ADC_DCCMP7_COMP1
Compare 1
16
26
DCCTL0
ADC Digital Comparator Control 0
0xE00
-1
read-write
n
0x0
0x0
ADC_DCCTL0_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL0_CIC_LOW
Low Band
0x0
ADC_DCCTL0_CIC_MID
Mid Band
0x1
ADC_DCCTL0_CIC_HIGH
High Band
0x3
ADC_DCCTL0_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL0_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL0_CIM_ALWAYS
Always
0x0
ADC_DCCTL0_CIM_ONCE
Once
0x1
ADC_DCCTL0_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL0_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL0_CTC_LOW
Low Band
0x0
ADC_DCCTL0_CTC_MID
Mid Band
0x1
ADC_DCCTL0_CTC_HIGH
High Band
0x3
ADC_DCCTL0_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL0_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL0_CTM_ALWAYS
Always
0x0
ADC_DCCTL0_CTM_ONCE
Once
0x1
ADC_DCCTL0_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL0_CTM_HONCE
Hysteresis Once
0x3
DCCTL1
ADC Digital Comparator Control 1
0xE04
-1
read-write
n
0x0
0x0
ADC_DCCTL1_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL1_CIC_LOW
Low Band
0x0
ADC_DCCTL1_CIC_MID
Mid Band
0x1
ADC_DCCTL1_CIC_HIGH
High Band
0x3
ADC_DCCTL1_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL1_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL1_CIM_ALWAYS
Always
0x0
ADC_DCCTL1_CIM_ONCE
Once
0x1
ADC_DCCTL1_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL1_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL1_CTC_LOW
Low Band
0x0
ADC_DCCTL1_CTC_MID
Mid Band
0x1
ADC_DCCTL1_CTC_HIGH
High Band
0x3
ADC_DCCTL1_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL1_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL1_CTM_ALWAYS
Always
0x0
ADC_DCCTL1_CTM_ONCE
Once
0x1
ADC_DCCTL1_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL1_CTM_HONCE
Hysteresis Once
0x3
DCCTL2
ADC Digital Comparator Control 2
0xE08
-1
read-write
n
0x0
0x0
ADC_DCCTL2_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL2_CIC_LOW
Low Band
0x0
ADC_DCCTL2_CIC_MID
Mid Band
0x1
ADC_DCCTL2_CIC_HIGH
High Band
0x3
ADC_DCCTL2_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL2_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL2_CIM_ALWAYS
Always
0x0
ADC_DCCTL2_CIM_ONCE
Once
0x1
ADC_DCCTL2_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL2_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL2_CTC_LOW
Low Band
0x0
ADC_DCCTL2_CTC_MID
Mid Band
0x1
ADC_DCCTL2_CTC_HIGH
High Band
0x3
ADC_DCCTL2_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL2_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL2_CTM_ALWAYS
Always
0x0
ADC_DCCTL2_CTM_ONCE
Once
0x1
ADC_DCCTL2_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL2_CTM_HONCE
Hysteresis Once
0x3
DCCTL3
ADC Digital Comparator Control 3
0xE0C
-1
read-write
n
0x0
0x0
ADC_DCCTL3_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL3_CIC_LOW
Low Band
0x0
ADC_DCCTL3_CIC_MID
Mid Band
0x1
ADC_DCCTL3_CIC_HIGH
High Band
0x3
ADC_DCCTL3_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL3_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL3_CIM_ALWAYS
Always
0x0
ADC_DCCTL3_CIM_ONCE
Once
0x1
ADC_DCCTL3_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL3_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL3_CTC_LOW
Low Band
0x0
ADC_DCCTL3_CTC_MID
Mid Band
0x1
ADC_DCCTL3_CTC_HIGH
High Band
0x3
ADC_DCCTL3_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL3_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL3_CTM_ALWAYS
Always
0x0
ADC_DCCTL3_CTM_ONCE
Once
0x1
ADC_DCCTL3_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL3_CTM_HONCE
Hysteresis Once
0x3
DCCTL4
ADC Digital Comparator Control 4
0xE10
-1
read-write
n
0x0
0x0
ADC_DCCTL4_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL4_CIC_LOW
Low Band
0x0
ADC_DCCTL4_CIC_MID
Mid Band
0x1
ADC_DCCTL4_CIC_HIGH
High Band
0x3
ADC_DCCTL4_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL4_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL4_CIM_ALWAYS
Always
0x0
ADC_DCCTL4_CIM_ONCE
Once
0x1
ADC_DCCTL4_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL4_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL4_CTC_LOW
Low Band
0x0
ADC_DCCTL4_CTC_MID
Mid Band
0x1
ADC_DCCTL4_CTC_HIGH
High Band
0x3
ADC_DCCTL4_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL4_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL4_CTM_ALWAYS
Always
0x0
ADC_DCCTL4_CTM_ONCE
Once
0x1
ADC_DCCTL4_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL4_CTM_HONCE
Hysteresis Once
0x3
DCCTL5
ADC Digital Comparator Control 5
0xE14
-1
read-write
n
0x0
0x0
ADC_DCCTL5_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL5_CIC_LOW
Low Band
0x0
ADC_DCCTL5_CIC_MID
Mid Band
0x1
ADC_DCCTL5_CIC_HIGH
High Band
0x3
ADC_DCCTL5_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL5_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL5_CIM_ALWAYS
Always
0x0
ADC_DCCTL5_CIM_ONCE
Once
0x1
ADC_DCCTL5_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL5_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL5_CTC_LOW
Low Band
0x0
ADC_DCCTL5_CTC_MID
Mid Band
0x1
ADC_DCCTL5_CTC_HIGH
High Band
0x3
ADC_DCCTL5_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL5_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL5_CTM_ALWAYS
Always
0x0
ADC_DCCTL5_CTM_ONCE
Once
0x1
ADC_DCCTL5_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL5_CTM_HONCE
Hysteresis Once
0x3
DCCTL6
ADC Digital Comparator Control 6
0xE18
-1
read-write
n
0x0
0x0
ADC_DCCTL6_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL6_CIC_LOW
Low Band
0x0
ADC_DCCTL6_CIC_MID
Mid Band
0x1
ADC_DCCTL6_CIC_HIGH
High Band
0x3
ADC_DCCTL6_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL6_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL6_CIM_ALWAYS
Always
0x0
ADC_DCCTL6_CIM_ONCE
Once
0x1
ADC_DCCTL6_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL6_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL6_CTC_LOW
Low Band
0x0
ADC_DCCTL6_CTC_MID
Mid Band
0x1
ADC_DCCTL6_CTC_HIGH
High Band
0x3
ADC_DCCTL6_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL6_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL6_CTM_ALWAYS
Always
0x0
ADC_DCCTL6_CTM_ONCE
Once
0x1
ADC_DCCTL6_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL6_CTM_HONCE
Hysteresis Once
0x3
DCCTL7
ADC Digital Comparator Control 7
0xE1C
-1
read-write
n
0x0
0x0
ADC_DCCTL7_CIC
Comparison Interrupt Condition
2
4
ADC_DCCTL7_CIC_LOW
Low Band
0x0
ADC_DCCTL7_CIC_MID
Mid Band
0x1
ADC_DCCTL7_CIC_HIGH
High Band
0x3
ADC_DCCTL7_CIE
Comparison Interrupt Enable
4
5
ADC_DCCTL7_CIM
Comparison Interrupt Mode
0
2
ADC_DCCTL7_CIM_ALWAYS
Always
0x0
ADC_DCCTL7_CIM_ONCE
Once
0x1
ADC_DCCTL7_CIM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CIM_HONCE
Hysteresis Once
0x3
ADC_DCCTL7_CTC
Comparison Trigger Condition
10
12
ADC_DCCTL7_CTC_LOW
Low Band
0x0
ADC_DCCTL7_CTC_MID
Mid Band
0x1
ADC_DCCTL7_CTC_HIGH
High Band
0x3
ADC_DCCTL7_CTE
Comparison Trigger Enable
12
13
ADC_DCCTL7_CTM
Comparison Trigger Mode
8
10
ADC_DCCTL7_CTM_ALWAYS
Always
0x0
ADC_DCCTL7_CTM_ONCE
Once
0x1
ADC_DCCTL7_CTM_HALWAYS
Hysteresis Always
0x2
ADC_DCCTL7_CTM_HONCE
Hysteresis Once
0x3
DCISC
ADC Digital Comparator Interrupt Status and Clear
0x34
-1
read-write
n
0x0
0x0
ADC_DCISC_DCINT0
Digital Comparator 0 Interrupt Status and Clear
0
1
ADC_DCISC_DCINT1
Digital Comparator 1 Interrupt Status and Clear
1
2
ADC_DCISC_DCINT2
Digital Comparator 2 Interrupt Status and Clear
2
3
ADC_DCISC_DCINT3
Digital Comparator 3 Interrupt Status and Clear
3
4
ADC_DCISC_DCINT4
Digital Comparator 4 Interrupt Status and Clear
4
5
ADC_DCISC_DCINT5
Digital Comparator 5 Interrupt Status and Clear
5
6
ADC_DCISC_DCINT6
Digital Comparator 6 Interrupt Status and Clear
6
7
ADC_DCISC_DCINT7
Digital Comparator 7 Interrupt Status and Clear
7
8
DCRIC
ADC Digital Comparator Reset Initial Conditions
0xD00
-1
read-write
n
0x0
0x0
ADC_DCRIC_DCINT0
Digital Comparator Interrupt 0
0
1
ADC_DCRIC_DCINT1
Digital Comparator Interrupt 1
1
2
ADC_DCRIC_DCINT2
Digital Comparator Interrupt 2
2
3
ADC_DCRIC_DCINT3
Digital Comparator Interrupt 3
3
4
ADC_DCRIC_DCINT4
Digital Comparator Interrupt 4
4
5
ADC_DCRIC_DCINT5
Digital Comparator Interrupt 5
5
6
ADC_DCRIC_DCINT6
Digital Comparator Interrupt 6
6
7
ADC_DCRIC_DCINT7
Digital Comparator Interrupt 7
7
8
ADC_DCRIC_DCTRIG0
Digital Comparator Trigger 0
16
17
ADC_DCRIC_DCTRIG1
Digital Comparator Trigger 1
17
18
ADC_DCRIC_DCTRIG2
Digital Comparator Trigger 2
18
19
ADC_DCRIC_DCTRIG3
Digital Comparator Trigger 3
19
20
ADC_DCRIC_DCTRIG4
Digital Comparator Trigger 4
20
21
ADC_DCRIC_DCTRIG5
Digital Comparator Trigger 5
21
22
ADC_DCRIC_DCTRIG6
Digital Comparator Trigger 6
22
23
ADC_DCRIC_DCTRIG7
Digital Comparator Trigger 7
23
24
EMUX
ADC Event Multiplexer Select
0x14
-1
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_PWM2
PWM2
0x8
ADC_EMUX_EM0_PWM3
PWM3
0x9
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_PWM2
PWM2
0x8
ADC_EMUX_EM1_PWM3
PWM3
0x9
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_PWM2
PWM2
0x8
ADC_EMUX_EM2_PWM3
PWM3
0x9
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_PWM2
PWM2
0x8
ADC_EMUX_EM3_PWM3
PWM3
0x9
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
IM
ADC Interrupt Mask
0x8
-1
read-write
n
0x0
0x0
ADC_IM_DCONSS0
Digital Comparator Interrupt on SS0
16
17
ADC_IM_DCONSS1
Digital Comparator Interrupt on SS1
17
18
ADC_IM_DCONSS2
Digital Comparator Interrupt on SS2
18
19
ADC_IM_DCONSS3
Digital Comparator Interrupt on SS3
19
20
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ISC
ADC Interrupt Status and Clear
0xC
-1
read-write
n
0x0
0x0
ADC_ISC_DCINSS0
Digital Comparator Interrupt Status on SS0
16
17
ADC_ISC_DCINSS1
Digital Comparator Interrupt Status on SS1
17
18
ADC_ISC_DCINSS2
Digital Comparator Interrupt Status on SS2
18
19
ADC_ISC_DCINSS3
Digital Comparator Interrupt Status on SS3
19
20
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
OSTAT
ADC Overflow Status
0x10
-1
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
PSSI
ADC Processor Sample Sequence Initiate
0x28
-1
read-write
n
0x0
0x0
ADC_PSSI_GSYNC
Global Synchronize
31
32
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
ADC_PSSI_SYNCWAIT
Synchronize Wait
27
28
RIS
ADC Raw Interrupt Status
0x4
-1
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
ADC_RIS_INRDC
Digital Comparator Raw Interrupt Status
16
17
SAC
ADC Sample Averaging Control
0x30
-1
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
SPC
ADC Sample Phase Control
0x24
-1
read-write
n
0x0
0x0
ADC_SPC_PHASE
Phase Difference
0
4
ADC_SPC_PHASE_0
ADC sample lags by 0.0
0x0
ADC_SPC_PHASE_22_5
ADC sample lags by 22.5
0x1
ADC_SPC_PHASE_45
ADC sample lags by 45.0
0x2
ADC_SPC_PHASE_67_5
ADC sample lags by 67.5
0x3
ADC_SPC_PHASE_90
ADC sample lags by 90.0
0x4
ADC_SPC_PHASE_112_5
ADC sample lags by 112.5
0x5
ADC_SPC_PHASE_135
ADC sample lags by 135.0
0x6
ADC_SPC_PHASE_157_5
ADC sample lags by 157.5
0x7
ADC_SPC_PHASE_180
ADC sample lags by 180.0
0x8
ADC_SPC_PHASE_202_5
ADC sample lags by 202.5
0x9
ADC_SPC_PHASE_225
ADC sample lags by 225.0
0xa
ADC_SPC_PHASE_247_5
ADC sample lags by 247.5
0xb
ADC_SPC_PHASE_270
ADC sample lags by 270.0
0xc
ADC_SPC_PHASE_292_5
ADC sample lags by 292.5
0xd
ADC_SPC_PHASE_315
ADC sample lags by 315.0
0xe
ADC_SPC_PHASE_337_5
ADC sample lags by 337.5
0xf
SSCTL0
ADC Sample Sequence Control 0
0x44
-1
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
SSCTL1
ADC Sample Sequence Control 1
0x64
-1
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
SSCTL2
ADC Sample Sequence Control 2
0x84
-1
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
SSCTL3
ADC Sample Sequence Control 3
0xA4
-1
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
SSDC0
ADC Sample Sequence 0 Digital Comparator Select
0x54
-1
read-write
n
0x0
0x0
ADC_SSDC0_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC0_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC0_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC0_S3DCSEL
Sample 3 Digital Comparator Select
12
16
ADC_SSDC0_S4DCSEL
Sample 4 Digital Comparator Select
16
20
ADC_SSDC0_S5DCSEL
Sample 5 Digital Comparator Select
20
24
ADC_SSDC0_S6DCSEL
Sample 6 Digital Comparator Select
24
28
ADC_SSDC0_S7DCSEL
Sample 7 Digital Comparator Select
28
32
SSDC1
ADC Sample Sequence 1 Digital Comparator Select
0x74
-1
read-write
n
0x0
0x0
ADC_SSDC1_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC1_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC1_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC1_S3DCSEL
Sample 3 Digital Comparator Select
12
16
SSDC2
ADC Sample Sequence 2 Digital Comparator Select
0x94
-1
read-write
n
0x0
0x0
ADC_SSDC2_S0DCSEL
Sample 0 Digital Comparator Select
0
4
ADC_SSDC2_S1DCSEL
Sample 1 Digital Comparator Select
4
8
ADC_SSDC2_S2DCSEL
Sample 2 Digital Comparator Select
8
12
ADC_SSDC2_S3DCSEL
Sample 3 Digital Comparator Select
12
16
SSDC3
ADC Sample Sequence 3 Digital Comparator Select
0xB4
-1
read-write
n
0x0
0x0
ADC_SSDC3_S0DCSEL
Sample 0 Digital Comparator Select
0
4
SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
-1
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
-1
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
-1
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
-1
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
-1
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
-1
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
4
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX0_MUX3
4th Sample Input Select
12
16
ADC_SSMUX0_MUX4
5th Sample Input Select
16
20
ADC_SSMUX0_MUX5
6th Sample Input Select
20
24
ADC_SSMUX0_MUX6
7th Sample Input Select
24
28
ADC_SSMUX0_MUX7
8th Sample Input Select
28
32
SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
-1
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
4
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX1_MUX3
4th Sample Input Select
12
16
SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
-1
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
4
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
8
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
12
ADC_SSMUX2_MUX3
4th Sample Input Select
12
16
SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
-1
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
4
SSOP0
ADC Sample Sequence 0 Operation
0x50
-1
read-write
n
0x0
0x0
ADC_SSOP0_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP0_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP0_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP0_S3DCOP
Sample 3 Digital Comparator Operation
12
13
ADC_SSOP0_S4DCOP
Sample 4 Digital Comparator Operation
16
17
ADC_SSOP0_S5DCOP
Sample 5 Digital Comparator Operation
20
21
ADC_SSOP0_S6DCOP
Sample 6 Digital Comparator Operation
24
25
ADC_SSOP0_S7DCOP
Sample 7 Digital Comparator Operation
28
29
SSOP1
ADC Sample Sequence 1 Operation
0x70
-1
read-write
n
0x0
0x0
ADC_SSOP1_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP1_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP1_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP1_S3DCOP
Sample 3 Digital Comparator Operation
12
13
SSOP2
ADC Sample Sequence 2 Operation
0x90
-1
read-write
n
0x0
0x0
ADC_SSOP2_S0DCOP
Sample 0 Digital Comparator Operation
0
1
ADC_SSOP2_S1DCOP
Sample 1 Digital Comparator Operation
4
5
ADC_SSOP2_S2DCOP
Sample 2 Digital Comparator Operation
8
9
ADC_SSOP2_S3DCOP
Sample 3 Digital Comparator Operation
12
13
SSOP3
ADC Sample Sequence 3 Operation
0xB0
-1
read-write
n
0x0
0x0
ADC_SSOP3_S0DCOP
Sample 0 Digital Comparator Operation
0
1
SSPRI
ADC Sample Sequencer Priority
0x20
-1
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
USTAT
ADC Underflow Status
0x18
-1
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
CAN0
Register map for CAN0 peripheral
CAN
0x0
0x0
0x1000
registers
n
BIT
CAN Bit Timing
0xC
-1
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
BRPE
CAN Baud Rate Prescaler Extension
0x18
-1
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0BIT
CAN Bit Timing
0xC
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
CAN0BRPE
CAN Baud Rate Prescaler Extension
0x18
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0CTL
CAN Control
0x0
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
CAN0ERR
CAN Error Counter
0x8
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
CAN0IF1ARB1
CAN IF1 Arbitration 1
0x30
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
CAN0IF1ARB2
CAN IF1 Arbitration 2
0x34
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
CAN0IF1CMSK
CAN IF1 Command Mask
0x24
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
CAN0IF1CRQ
CAN IF1 Command Request
0x20
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF1DA1
CAN IF1 Data A1
0x3C
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
CAN0IF1DA2
CAN IF1 Data A2
0x40
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
CAN0IF1DB1
CAN IF1 Data B1
0x44
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
CAN0IF1DB2
CAN IF1 Data B2
0x48
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
CAN0IF1MCTL
CAN IF1 Message Control
0x38
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF1MSK1
CAN IF1 Mask 1
0x28
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
CAN0IF1MSK2
CAN IF1 Mask 2
0x2C
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
CAN0IF2ARB1
CAN IF2 Arbitration 1
0x90
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
CAN0IF2ARB2
CAN IF2 Arbitration 2
0x94
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
CAN0IF2CMSK
CAN IF2 Command Mask
0x84
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
CAN0IF2CRQ
CAN IF2 Command Request
0x80
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF2DA1
CAN IF2 Data A1
0x9C
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
CAN0IF2DA2
CAN IF2 Data A2
0xA0
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
CAN0IF2DB1
CAN IF2 Data B1
0xA4
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
CAN0IF2DB2
CAN IF2 Data B2
0xA8
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
CAN0IF2MCTL
CAN IF2 Message Control
0x98
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF2MSK1
CAN IF2 Mask 1
0x88
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
CAN0IF2MSK2
CAN IF2 Mask 2
0x8C
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
CAN0INT
CAN Interrupt
0x10
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
CAN0MSG1INT
CAN Message 1 Interrupt Pending
0x140
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG1VAL
CAN Message 1 Valid
0x160
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
CAN0MSG2INT
CAN Message 2 Interrupt Pending
0x144
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG2VAL
CAN Message 2 Valid
0x164
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
CAN0NWDA1
CAN New Data 1
0x120
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
CAN0NWDA2
CAN New Data 2
0x124
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
CAN0STS
CAN Status
0x4
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
CAN0TST
CAN Test
0x14
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
CAN0TXRQ1
CAN Transmission Request 1
0x100
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
CAN0TXRQ2
CAN Transmission Request 2
0x104
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
CTL
CAN Control
0x0
-1
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
ERR
CAN Error Counter
0x8
-1
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
IF1ARB1
CAN IF1 Arbitration 1
0x30
-1
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
IF1ARB2
CAN IF1 Arbitration 2
0x34
-1
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
IF1CMSK
CAN IF1 Command Mask
0x24
-1
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
IF1CRQ
CAN IF1 Command Request
0x20
-1
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF1DA1
CAN IF1 Data A1
0x3C
-1
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
IF1DA2
CAN IF1 Data A2
0x40
-1
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
IF1DB1
CAN IF1 Data B1
0x44
-1
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
IF1DB2
CAN IF1 Data B2
0x48
-1
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
IF1MCTL
CAN IF1 Message Control
0x38
-1
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
IF1MSK1
CAN IF1 Mask 1
0x28
-1
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
IF1MSK2
CAN IF1 Mask 2
0x2C
-1
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
IF2ARB1
CAN IF2 Arbitration 1
0x90
-1
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
IF2ARB2
CAN IF2 Arbitration 2
0x94
-1
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
IF2CMSK
CAN IF2 Command Mask
0x84
-1
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
IF2CRQ
CAN IF2 Command Request
0x80
-1
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF2DA1
CAN IF2 Data A1
0x9C
-1
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
IF2DA2
CAN IF2 Data A2
0xA0
-1
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
IF2DB1
CAN IF2 Data B1
0xA4
-1
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
IF2DB2
CAN IF2 Data B2
0xA8
-1
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
IF2MCTL
CAN IF2 Message Control
0x98
-1
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
IF2MSK1
CAN IF2 Mask 1
0x88
-1
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
IF2MSK2
CAN IF2 Mask 2
0x8C
-1
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
INT
CAN Interrupt
0x10
-1
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
MSG1INT
CAN Message 1 Interrupt Pending
0x140
-1
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
MSG1VAL
CAN Message 1 Valid
0x160
-1
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
MSG2INT
CAN Message 2 Interrupt Pending
0x144
-1
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
MSG2VAL
CAN Message 2 Valid
0x164
-1
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
NWDA1
CAN New Data 1
0x120
-1
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
NWDA2
CAN New Data 2
0x124
-1
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
STS
CAN Status
0x4
-1
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
TST
CAN Test
0x14
-1
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
TXRQ1
CAN Transmission Request 1
0x100
-1
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
TXRQ2
CAN Transmission Request 2
0x104
-1
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
CAN1
Register map for CAN0 peripheral
CAN
0x0
0x0
0x1000
registers
n
BIT
CAN Bit Timing
0xC
-1
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
BRPE
CAN Baud Rate Prescaler Extension
0x18
-1
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0BIT
CAN Bit Timing
0xC
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
CAN0BRPE
CAN Baud Rate Prescaler Extension
0x18
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0CTL
CAN Control
0x0
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
CAN0ERR
CAN Error Counter
0x8
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
CAN0IF1ARB1
CAN IF1 Arbitration 1
0x30
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
CAN0IF1ARB2
CAN IF1 Arbitration 2
0x34
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
CAN0IF1CMSK
CAN IF1 Command Mask
0x24
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
CAN0IF1CRQ
CAN IF1 Command Request
0x20
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF1DA1
CAN IF1 Data A1
0x3C
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
CAN0IF1DA2
CAN IF1 Data A2
0x40
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
CAN0IF1DB1
CAN IF1 Data B1
0x44
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
CAN0IF1DB2
CAN IF1 Data B2
0x48
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
CAN0IF1MCTL
CAN IF1 Message Control
0x38
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF1MSK1
CAN IF1 Mask 1
0x28
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
CAN0IF1MSK2
CAN IF1 Mask 2
0x2C
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
CAN0IF2ARB1
CAN IF2 Arbitration 1
0x90
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
CAN0IF2ARB2
CAN IF2 Arbitration 2
0x94
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
CAN0IF2CMSK
CAN IF2 Command Mask
0x84
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
CAN0IF2CRQ
CAN IF2 Command Request
0x80
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF2DA1
CAN IF2 Data A1
0x9C
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
CAN0IF2DA2
CAN IF2 Data A2
0xA0
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
CAN0IF2DB1
CAN IF2 Data B1
0xA4
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
CAN0IF2DB2
CAN IF2 Data B2
0xA8
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
CAN0IF2MCTL
CAN IF2 Message Control
0x98
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF2MSK1
CAN IF2 Mask 1
0x88
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
CAN0IF2MSK2
CAN IF2 Mask 2
0x8C
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
CAN0INT
CAN Interrupt
0x10
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
CAN0MSG1INT
CAN Message 1 Interrupt Pending
0x140
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG1VAL
CAN Message 1 Valid
0x160
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
CAN0MSG2INT
CAN Message 2 Interrupt Pending
0x144
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG2VAL
CAN Message 2 Valid
0x164
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
CAN0NWDA1
CAN New Data 1
0x120
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
CAN0NWDA2
CAN New Data 2
0x124
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
CAN0STS
CAN Status
0x4
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
CAN0TST
CAN Test
0x14
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
CAN0TXRQ1
CAN Transmission Request 1
0x100
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
CAN0TXRQ2
CAN Transmission Request 2
0x104
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
CTL
CAN Control
0x0
-1
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
ERR
CAN Error Counter
0x8
-1
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
IF1ARB1
CAN IF1 Arbitration 1
0x30
-1
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
IF1ARB2
CAN IF1 Arbitration 2
0x34
-1
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
IF1CMSK
CAN IF1 Command Mask
0x24
-1
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
IF1CRQ
CAN IF1 Command Request
0x20
-1
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF1DA1
CAN IF1 Data A1
0x3C
-1
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
IF1DA2
CAN IF1 Data A2
0x40
-1
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
IF1DB1
CAN IF1 Data B1
0x44
-1
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
IF1DB2
CAN IF1 Data B2
0x48
-1
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
IF1MCTL
CAN IF1 Message Control
0x38
-1
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
IF1MSK1
CAN IF1 Mask 1
0x28
-1
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
IF1MSK2
CAN IF1 Mask 2
0x2C
-1
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
IF2ARB1
CAN IF2 Arbitration 1
0x90
-1
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
IF2ARB2
CAN IF2 Arbitration 2
0x94
-1
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
IF2CMSK
CAN IF2 Command Mask
0x84
-1
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
IF2CRQ
CAN IF2 Command Request
0x80
-1
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF2DA1
CAN IF2 Data A1
0x9C
-1
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
IF2DA2
CAN IF2 Data A2
0xA0
-1
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
IF2DB1
CAN IF2 Data B1
0xA4
-1
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
IF2DB2
CAN IF2 Data B2
0xA8
-1
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
IF2MCTL
CAN IF2 Message Control
0x98
-1
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
IF2MSK1
CAN IF2 Mask 1
0x88
-1
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
IF2MSK2
CAN IF2 Mask 2
0x8C
-1
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
INT
CAN Interrupt
0x10
-1
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
MSG1INT
CAN Message 1 Interrupt Pending
0x140
-1
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
MSG1VAL
CAN Message 1 Valid
0x160
-1
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
MSG2INT
CAN Message 2 Interrupt Pending
0x144
-1
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
MSG2VAL
CAN Message 2 Valid
0x164
-1
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
NWDA1
CAN New Data 1
0x120
-1
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
NWDA2
CAN New Data 2
0x124
-1
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
STS
CAN Status
0x4
-1
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
TST
CAN Test
0x14
-1
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
TXRQ1
CAN Transmission Request 1
0x100
-1
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
TXRQ2
CAN Transmission Request 2
0x104
-1
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
COMP
Register map for COMP peripheral
COMP
0x0
0x0
0x1000
registers
n
ACCTL0
Analog Comparator Control 0
0x24
-1
read-write
n
0x0
0x0
COMP_ACCTL0_ASRCP
Analog Source Positive
9
11
COMP_ACCTL0_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL0_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL0_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL0_CINV
Comparator Output Invert
1
2
COMP_ACCTL0_ISEN
Interrupt Sense
2
4
COMP_ACCTL0_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL0_ISEN_FALL
Falling edge
0x1
COMP_ACCTL0_ISEN_RISE
Rising edge
0x2
COMP_ACCTL0_ISEN_BOTH
Either edge
0x3
COMP_ACCTL0_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL0_TOEN
Trigger Output Enable
11
12
COMP_ACCTL0_TSEN
Trigger Sense
5
7
COMP_ACCTL0_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL0_TSEN_FALL
Falling edge
0x1
COMP_ACCTL0_TSEN_RISE
Rising edge
0x2
COMP_ACCTL0_TSEN_BOTH
Either edge
0x3
COMP_ACCTL0_TSLVAL
Trigger Sense Level Value
7
8
ACCTL1
Analog Comparator Control 1
0x44
-1
read-write
n
0x0
0x0
COMP_ACCTL1_ASRCP
Analog Source Positive
9
11
COMP_ACCTL1_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL1_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL1_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL1_CINV
Comparator Output Invert
1
2
COMP_ACCTL1_ISEN
Interrupt Sense
2
4
COMP_ACCTL1_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL1_ISEN_FALL
Falling edge
0x1
COMP_ACCTL1_ISEN_RISE
Rising edge
0x2
COMP_ACCTL1_ISEN_BOTH
Either edge
0x3
COMP_ACCTL1_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL1_TOEN
Trigger Output Enable
11
12
COMP_ACCTL1_TSEN
Trigger Sense
5
7
COMP_ACCTL1_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL1_TSEN_FALL
Falling edge
0x1
COMP_ACCTL1_TSEN_RISE
Rising edge
0x2
COMP_ACCTL1_TSEN_BOTH
Either edge
0x3
COMP_ACCTL1_TSLVAL
Trigger Sense Level Value
7
8
ACINTEN
Analog Comparator Interrupt Enable
0x8
-1
read-write
n
0x0
0x0
COMP_ACINTEN_IN0
Comparator 0 Interrupt Enable
0
1
COMP_ACINTEN_IN1
Comparator 1 Interrupt Enable
1
2
ACMIS
Analog Comparator Masked Interrupt Status
0x0
-1
read-write
n
0x0
0x0
COMP_ACMIS_IN0
Comparator 0 Masked Interrupt Status
0
1
COMP_ACMIS_IN1
Comparator 1 Masked Interrupt Status
1
2
ACREFCTL
Analog Comparator Reference Voltage Control
0x10
-1
read-write
n
0x0
0x0
COMP_ACREFCTL_EN
Resistor Ladder Enable
9
10
COMP_ACREFCTL_RNG
Resistor Ladder Range
8
9
COMP_ACREFCTL_VREF
Resistor Ladder Voltage Ref
0
4
ACRIS
Analog Comparator Raw Interrupt Status
0x4
-1
read-write
n
0x0
0x0
COMP_ACRIS_IN0
Comparator 0 Interrupt Status
0
1
COMP_ACRIS_IN1
Comparator 1 Interrupt Status
1
2
ACSTAT0
Analog Comparator Status 0
0x20
-1
read-write
n
0x0
0x0
COMP_ACSTAT0_OVAL
Comparator Output Value
1
2
ACSTAT1
Analog Comparator Status 1
0x40
-1
read-write
n
0x0
0x0
COMP_ACSTAT1_OVAL
Comparator Output Value
1
2
COMPACCTL0
Analog Comparator Control 0
0x24
read-write
n
0x0
0x0
COMP_ACCTL0_ASRCP
Analog Source Positive
9
11
COMP_ACCTL0_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL0_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL0_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL0_CINV
Comparator Output Invert
1
2
COMP_ACCTL0_ISEN
Interrupt Sense
2
4
COMP_ACCTL0_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL0_ISEN_FALL
Falling edge
0x1
COMP_ACCTL0_ISEN_RISE
Rising edge
0x2
COMP_ACCTL0_ISEN_BOTH
Either edge
0x3
COMP_ACCTL0_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL0_TOEN
Trigger Output Enable
11
12
COMP_ACCTL0_TSEN
Trigger Sense
5
7
COMP_ACCTL0_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL0_TSEN_FALL
Falling edge
0x1
COMP_ACCTL0_TSEN_RISE
Rising edge
0x2
COMP_ACCTL0_TSEN_BOTH
Either edge
0x3
COMP_ACCTL0_TSLVAL
Trigger Sense Level Value
7
8
COMPACCTL1
Analog Comparator Control 1
0x44
read-write
n
0x0
0x0
COMP_ACCTL1_ASRCP
Analog Source Positive
9
11
COMP_ACCTL1_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL1_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL1_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL1_CINV
Comparator Output Invert
1
2
COMP_ACCTL1_ISEN
Interrupt Sense
2
4
COMP_ACCTL1_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL1_ISEN_FALL
Falling edge
0x1
COMP_ACCTL1_ISEN_RISE
Rising edge
0x2
COMP_ACCTL1_ISEN_BOTH
Either edge
0x3
COMP_ACCTL1_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL1_TOEN
Trigger Output Enable
11
12
COMP_ACCTL1_TSEN
Trigger Sense
5
7
COMP_ACCTL1_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL1_TSEN_FALL
Falling edge
0x1
COMP_ACCTL1_TSEN_RISE
Rising edge
0x2
COMP_ACCTL1_TSEN_BOTH
Either edge
0x3
COMP_ACCTL1_TSLVAL
Trigger Sense Level Value
7
8
COMPACINTEN
Analog Comparator Interrupt Enable
0x8
read-write
n
0x0
0x0
COMP_ACINTEN_IN0
Comparator 0 Interrupt Enable
0
1
COMP_ACINTEN_IN1
Comparator 1 Interrupt Enable
1
2
COMPACMIS
Analog Comparator Masked Interrupt Status
0x0
read-write
n
0x0
0x0
COMP_ACMIS_IN0
Comparator 0 Masked Interrupt Status
0
1
COMP_ACMIS_IN1
Comparator 1 Masked Interrupt Status
1
2
COMPACREFCTL
Analog Comparator Reference Voltage Control
0x10
read-write
n
0x0
0x0
COMP_ACREFCTL_EN
Resistor Ladder Enable
9
10
COMP_ACREFCTL_RNG
Resistor Ladder Range
8
9
COMP_ACREFCTL_VREF
Resistor Ladder Voltage Ref
0
4
COMPACRIS
Analog Comparator Raw Interrupt Status
0x4
read-write
n
0x0
0x0
COMP_ACRIS_IN0
Comparator 0 Interrupt Status
0
1
COMP_ACRIS_IN1
Comparator 1 Interrupt Status
1
2
COMPACSTAT0
Analog Comparator Status 0
0x20
read-write
n
0x0
0x0
COMP_ACSTAT0_OVAL
Comparator Output Value
1
2
COMPACSTAT1
Analog Comparator Status 1
0x40
read-write
n
0x0
0x0
COMP_ACSTAT1_OVAL
Comparator Output Value
1
2
FLASH_CTRL
Register map for FLASH_CTRL peripheral
FLASH_CTRL
0x0
0x0
0x1000
registers
n
0x1000
0x1000
registers
n
BOOTCFG
Boot Configuration
0x11D0
-1
read-write
n
0x0
0x0
FLASH_BOOTCFG_DBG0
Debug Control 0
0
1
FLASH_BOOTCFG_DBG1
Debug Control 1
1
2
FLASH_BOOTCFG_EN
Boot GPIO Enable
8
9
FLASH_BOOTCFG_NW
Not Written
31
32
FLASH_BOOTCFG_PIN
Boot GPIO Pin
10
13
FLASH_BOOTCFG_PIN_0
Pin 0
0x0
FLASH_BOOTCFG_PIN_1
Pin 1
0x1
FLASH_BOOTCFG_PIN_2
Pin 2
0x2
FLASH_BOOTCFG_PIN_3
Pin 3
0x3
FLASH_BOOTCFG_PIN_4
Pin 4
0x4
FLASH_BOOTCFG_PIN_5
Pin 5
0x5
FLASH_BOOTCFG_PIN_6
Pin 6
0x6
FLASH_BOOTCFG_PIN_7
Pin 7
0x7
FLASH_BOOTCFG_POL
Boot GPIO Polarity
9
10
FLASH_BOOTCFG_PORT
Boot GPIO Port
13
16
FLASH_BOOTCFG_PORT_A
Port A
0x0
FLASH_BOOTCFG_PORT_B
Port B
0x1
FLASH_BOOTCFG_PORT_C
Port C
0x2
FLASH_BOOTCFG_PORT_D
Port D
0x3
FLASH_BOOTCFG_PORT_E
Port E
0x4
FLASH_BOOTCFG_PORT_F
Port F
0x5
FLASH_BOOTCFG_PORT_G
Port G
0x6
FLASH_BOOTCFG_PORT_H
Port H
0x7
FCIM
Flash Controller Interrupt Mask
0x10
-1
read-write
n
0x0
0x0
FLASH_FCIM_AMASK
Access Interrupt Mask
0
1
FLASH_FCIM_PMASK
Programming Interrupt Mask
1
2
FCMISC
Flash Controller Masked Interrupt Status and Clear
0x14
-1
read-write
n
0x0
0x0
FLASH_FCMISC_AMISC
Access Masked Interrupt Status and Clear
0
1
FLASH_FCMISC_PMISC
Programming Masked Interrupt Status and Clear
1
2
FCRIS
Flash Controller Raw Interrupt Status
0xC
-1
read-write
n
0x0
0x0
FLASH_FCRIS_ARIS
Access Raw Interrupt Status
0
1
FLASH_FCRIS_PRIS
Programming Raw Interrupt Status
1
2
FCTL
Flash Control
0xF8
-1
read-write
n
0x0
0x0
FLASH_FCTL_USDACK
User Shut Down Acknowledge
1
2
FLASH_FCTL_USDREQ
User Shut Down Request
0
1
FLASH_CTRLBOOTCFG
Boot Configuration
0x11D0
read-write
n
0x0
0x0
FLASH_BOOTCFG_DBG0
Debug Control 0
0
1
FLASH_BOOTCFG_DBG1
Debug Control 1
1
2
FLASH_BOOTCFG_EN
Boot GPIO Enable
8
9
FLASH_BOOTCFG_NW
Not Written
31
32
FLASH_BOOTCFG_PIN
Boot GPIO Pin
10
13
FLASH_BOOTCFG_PIN_0
Pin 0
0x0
FLASH_BOOTCFG_PIN_1
Pin 1
0x1
FLASH_BOOTCFG_PIN_2
Pin 2
0x2
FLASH_BOOTCFG_PIN_3
Pin 3
0x3
FLASH_BOOTCFG_PIN_4
Pin 4
0x4
FLASH_BOOTCFG_PIN_5
Pin 5
0x5
FLASH_BOOTCFG_PIN_6
Pin 6
0x6
FLASH_BOOTCFG_PIN_7
Pin 7
0x7
FLASH_BOOTCFG_POL
Boot GPIO Polarity
9
10
FLASH_BOOTCFG_PORT
Boot GPIO Port
13
16
FLASH_BOOTCFG_PORT_A
Port A
0x0
FLASH_BOOTCFG_PORT_B
Port B
0x1
FLASH_BOOTCFG_PORT_C
Port C
0x2
FLASH_BOOTCFG_PORT_D
Port D
0x3
FLASH_BOOTCFG_PORT_E
Port E
0x4
FLASH_BOOTCFG_PORT_F
Port F
0x5
FLASH_BOOTCFG_PORT_G
Port G
0x6
FLASH_BOOTCFG_PORT_H
Port H
0x7
FLASH_CTRLFCIM
Flash Controller Interrupt Mask
0x10
read-write
n
0x0
0x0
FLASH_FCIM_AMASK
Access Interrupt Mask
0
1
FLASH_FCIM_PMASK
Programming Interrupt Mask
1
2
FLASH_CTRLFCMISC
Flash Controller Masked Interrupt Status and Clear
0x14
read-write
n
0x0
0x0
FLASH_FCMISC_AMISC
Access Masked Interrupt Status and Clear
0
1
FLASH_FCMISC_PMISC
Programming Masked Interrupt Status and Clear
1
2
FLASH_CTRLFCRIS
Flash Controller Raw Interrupt Status
0xC
read-write
n
0x0
0x0
FLASH_FCRIS_ARIS
Access Raw Interrupt Status
0
1
FLASH_FCRIS_PRIS
Programming Raw Interrupt Status
1
2
FLASH_CTRLFCTL
Flash Control
0xF8
read-write
n
0x0
0x0
FLASH_FCTL_USDACK
User Shut Down Acknowledge
1
2
FLASH_FCTL_USDREQ
User Shut Down Request
0
1
FLASH_CTRLFMA
Flash Memory Address
0x0
read-write
n
0x0
0x0
FLASH_FMA_OFFSET
Address Offset
0
18
FLASH_CTRLFMC
Flash Memory Control
0x8
read-write
n
0x0
0x0
FLASH_FMC_COMT
Commit Register Value
3
4
FLASH_FMC_ERASE
Erase a Page of Flash Memory
1
2
FLASH_FMC_MERASE
Mass Erase Flash Memory
2
3
FLASH_FMC_WRITE
Write a Word into Flash Memory
0
1
FLASH_FMC_WRKEY
FLASH write key
17
32
FLASH_CTRLFMC2
Flash Memory Control 2
0x20
read-write
n
0x0
0x0
FLASH_FMC2_WRBUF
Buffered Flash Memory Write
0
1
FLASH_FMC2_WRKEY
FLASH write key
17
32
FLASH_CTRLFMD
Flash Memory Data
0x4
read-write
n
0x0
0x0
FLASH_FMD_DATA
Data Value
0
32
FLASH_CTRLFMPPE0
Flash Memory Protection Program Enable 0
0x1400
read-write
n
0x0
0x0
FLASH_CTRLFMPPE1
Flash Memory Protection Program Enable 1
0x1404
read-write
n
0x0
0x0
FLASH_CTRLFMPPE2
Flash Memory Protection Program Enable 2
0x1408
read-write
n
0x0
0x0
FLASH_CTRLFMPPE3
Flash Memory Protection Program Enable 3
0x140C
read-write
n
0x0
0x0
FLASH_CTRLFMPRE0
Flash Memory Protection Read Enable 0
0x1200
read-write
n
0x0
0x0
FLASH_CTRLFMPRE1
Flash Memory Protection Read Enable 1
0x1204
read-write
n
0x0
0x0
FLASH_CTRLFMPRE2
Flash Memory Protection Read Enable 2
0x1208
read-write
n
0x0
0x0
FLASH_CTRLFMPRE3
Flash Memory Protection Read Enable 3
0x120C
read-write
n
0x0
0x0
FLASH_CTRLFWBN
Flash Write Buffer n
0x100
read-write
n
0x0
0x0
FLASH_FWBN_DATA
Data
0
32
FLASH_CTRLFWBVAL
Flash Write Buffer Valid
0x30
read-write
n
0x0
0x0
FLASH_FWBVAL_FWB
Flash Memory Write Buffer
0
32
FLASH_CTRLRMCTL
ROM Control
0x10F0
read-write
n
0x0
0x0
FLASH_RMCTL_BA
Boot Alias
0
1
FLASH_CTRLUSERDBG
User Debug
FLASH_ALT
0x11D0
read-write
n
0x0
0x0
FLASH_USERDBG_DATA
User Data
2
31
FLASH_USERDBG_DBG0
Debug Control 0
0
1
FLASH_USERDBG_DBG1
Debug Control 1
1
2
FLASH_USERDBG_NW
User Debug Not Written
31
32
FLASH_CTRLUSERREG0
User Register 0
0x11E0
read-write
n
0x0
0x0
FLASH_USERREG0_DATA
User Data
0
31
FLASH_USERREG0_NW
Not Written
31
32
FLASH_CTRLUSERREG1
User Register 1
0x11E4
read-write
n
0x0
0x0
FLASH_USERREG1_DATA
User Data
0
31
FLASH_USERREG1_NW
Not Written
31
32
FLASH_CTRLUSERREG2
User Register 2
0x11E8
read-write
n
0x0
0x0
FLASH_USERREG2_DATA
User Data
0
31
FLASH_USERREG2_NW
Not Written
31
32
FLASH_CTRLUSERREG3
User Register 3
0x11EC
read-write
n
0x0
0x0
FLASH_USERREG3_DATA
User Data
0
31
FLASH_USERREG3_NW
Not Written
31
32
FMA
Flash Memory Address
0x0
-1
read-write
n
0x0
0x0
FLASH_FMA_OFFSET
Address Offset
0
18
FMC
Flash Memory Control
0x8
-1
read-write
n
0x0
0x0
FLASH_FMC_COMT
Commit Register Value
3
4
FLASH_FMC_ERASE
Erase a Page of Flash Memory
1
2
FLASH_FMC_MERASE
Mass Erase Flash Memory
2
3
FLASH_FMC_WRITE
Write a Word into Flash Memory
0
1
FLASH_FMC_WRKEY
FLASH write key
17
32
FMC2
Flash Memory Control 2
0x20
-1
read-write
n
0x0
0x0
FLASH_FMC2_WRBUF
Buffered Flash Memory Write
0
1
FLASH_FMC2_WRKEY
FLASH write key
17
32
FMD
Flash Memory Data
0x4
-1
read-write
n
0x0
0x0
FLASH_FMD_DATA
Data Value
0
32
FMPPE0
Flash Memory Protection Program Enable 0
0x1400
-1
read-write
n
0x0
0x0
FMPPE1
Flash Memory Protection Program Enable 1
0x1404
-1
read-write
n
0x0
0x0
FMPPE2
Flash Memory Protection Program Enable 2
0x1408
-1
read-write
n
0x0
0x0
FMPPE3
Flash Memory Protection Program Enable 3
0x140C
-1
read-write
n
0x0
0x0
FMPRE0
Flash Memory Protection Read Enable 0
0x1200
-1
read-write
n
0x0
0x0
FMPRE1
Flash Memory Protection Read Enable 1
0x1204
-1
read-write
n
0x0
0x0
FMPRE2
Flash Memory Protection Read Enable 2
0x1208
-1
read-write
n
0x0
0x0
FMPRE3
Flash Memory Protection Read Enable 3
0x120C
-1
read-write
n
0x0
0x0
FWBN
Flash Write Buffer n
0x100
-1
read-write
n
0x0
0x0
FLASH_FWBN_DATA
Data
0
32
FWBVAL
Flash Write Buffer Valid
0x30
-1
read-write
n
0x0
0x0
FLASH_FWBVAL_FWB
Flash Memory Write Buffer
0
32
RMCTL
ROM Control
0x10F0
-1
read-write
n
0x0
0x0
FLASH_RMCTL_BA
Boot Alias
0
1
USERDBG
User Debug
0x11D0
-1
read-write
n
0x0
0x0
FLASH_USERDBG_DATA
User Data
2
31
FLASH_USERDBG_DBG0
Debug Control 0
0
1
FLASH_USERDBG_DBG1
Debug Control 1
1
2
FLASH_USERDBG_NW
User Debug Not Written
31
32
USERREG0
User Register 0
0x11E0
-1
read-write
n
0x0
0x0
FLASH_USERREG0_DATA
User Data
0
31
FLASH_USERREG0_NW
Not Written
31
32
USERREG1
User Register 1
0x11E4
-1
read-write
n
0x0
0x0
FLASH_USERREG1_DATA
User Data
0
31
FLASH_USERREG1_NW
Not Written
31
32
USERREG2
User Register 2
0x11E8
-1
read-write
n
0x0
0x0
FLASH_USERREG2_DATA
User Data
0
31
FLASH_USERREG2_NW
Not Written
31
32
USERREG3
User Register 3
0x11EC
-1
read-write
n
0x0
0x0
FLASH_USERREG3_DATA
User Data
0
31
FLASH_USERREG3_NW
Not Written
31
32
GPIO_PORTA
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTA_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTB_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTC
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTC_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTD
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTD_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTE
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTE_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTF
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTF_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTG
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTG_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTH
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTH_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTJ
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTJ_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPCTL
GPIO Port Control
0x52C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PCTL
GPIO Port Control
0x52C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
HIB
Register map for HIB peripheral
HIB
0x0
0x0
0x1000
registers
n
CTL
Hibernation Control
0x10
-1
read-write
n
0x0
0x0
HIB_CTL_CLK32EN
Clocking Enable
6
7
HIB_CTL_CLKSEL
Hibernation Module Clock Select
2
3
HIB_CTL_HIBREQ
Hibernation Request
1
2
HIB_CTL_LOWBATEN
Low Battery Monitoring Enable
5
6
HIB_CTL_PINWEN
External WAKE Pin Enable
4
5
HIB_CTL_RTCEN
RTC Timer Enable
0
1
HIB_CTL_RTCWEN
RTC Wake-up Enable
3
4
HIB_CTL_VABORT
Power Cut Abort Enable
7
8
HIB_CTL_VDD3ON
VDD Powered
8
9
HIB_CTL_WRC
Write Complete/Capable
31
32
DATA
Hibernation Data
0x30
-1
read-write
n
0x0
0x0
HIB_DATA_RTD
Hibernation Module NV Data
0
32
HIBCTL
Hibernation Control
0x10
read-write
n
0x0
0x0
HIB_CTL_CLK32EN
Clocking Enable
6
7
HIB_CTL_CLKSEL
Hibernation Module Clock Select
2
3
HIB_CTL_HIBREQ
Hibernation Request
1
2
HIB_CTL_LOWBATEN
Low Battery Monitoring Enable
5
6
HIB_CTL_PINWEN
External WAKE Pin Enable
4
5
HIB_CTL_RTCEN
RTC Timer Enable
0
1
HIB_CTL_RTCWEN
RTC Wake-up Enable
3
4
HIB_CTL_VABORT
Power Cut Abort Enable
7
8
HIB_CTL_VDD3ON
VDD Powered
8
9
HIB_CTL_WRC
Write Complete/Capable
31
32
HIBDATA
Hibernation Data
0x30
read-write
n
0x0
0x0
HIB_DATA_RTD
Hibernation Module NV Data
0
32
HIBIC
Hibernation Interrupt Clear
0x20
read-write
n
0x0
0x0
HIB_IC_EXTW
External Wake-Up Masked Interrupt Clear
3
4
HIB_IC_LOWBAT
Low Battery Voltage Masked Interrupt Clear
2
3
HIB_IC_RTCALT0
RTC Alert0 Masked Interrupt Clear
0
1
HIB_IC_RTCALT1
RTC Alert1 Masked Interrupt Clear
1
2
HIBIM
Hibernation Interrupt Mask
0x14
read-write
n
0x0
0x0
HIB_IM_EXTW
External Wake-Up Interrupt Mask
3
4
HIB_IM_LOWBAT
Low Battery Voltage Interrupt Mask
2
3
HIB_IM_RTCALT0
RTC Alert 0 Interrupt Mask
0
1
HIB_IM_RTCALT1
RTC Alert 1 Interrupt Mask
1
2
HIBMIS
Hibernation Masked Interrupt Status
0x1C
read-write
n
0x0
0x0
HIB_MIS_EXTW
External Wake-Up Masked Interrupt Status
3
4
HIB_MIS_LOWBAT
Low Battery Voltage Masked Interrupt Status
2
3
HIB_MIS_RTCALT0
RTC Alert 0 Masked Interrupt Status
0
1
HIB_MIS_RTCALT1
RTC Alert 1 Masked Interrupt Status
1
2
HIBRIS
Hibernation Raw Interrupt Status
0x18
read-write
n
0x0
0x0
HIB_RIS_EXTW
External Wake-Up Raw Interrupt Status
3
4
HIB_RIS_LOWBAT
Low Battery Voltage Raw Interrupt Status
2
3
HIB_RIS_RTCALT0
RTC Alert 0 Raw Interrupt Status
0
1
HIB_RIS_RTCALT1
RTC Alert 1 Raw Interrupt Status
1
2
HIBRTCC
Hibernation RTC Counter
0x0
read-write
n
0x0
0x0
HIB_RTCC
RTC Counter
0
32
HIBRTCLD
Hibernation RTC Load
0xC
read-write
n
0x0
0x0
HIB_RTCLD
RTC Load
0
32
HIBRTCM0
Hibernation RTC Match 0
0x4
read-write
n
0x0
0x0
HIB_RTCM0
RTC Match 0
0
32
HIBRTCM1
Hibernation RTC Match 1
0x8
read-write
n
0x0
0x0
HIB_RTCM1
RTC Match 1
0
32
HIBRTCT
Hibernation RTC Trim
0x24
read-write
n
0x0
0x0
HIB_RTCT_TRIM
RTC Trim Value
0
16
IC
Hibernation Interrupt Clear
0x20
-1
read-write
n
0x0
0x0
HIB_IC_EXTW
External Wake-Up Masked Interrupt Clear
3
4
HIB_IC_LOWBAT
Low Battery Voltage Masked Interrupt Clear
2
3
HIB_IC_RTCALT0
RTC Alert0 Masked Interrupt Clear
0
1
HIB_IC_RTCALT1
RTC Alert1 Masked Interrupt Clear
1
2
IM
Hibernation Interrupt Mask
0x14
-1
read-write
n
0x0
0x0
HIB_IM_EXTW
External Wake-Up Interrupt Mask
3
4
HIB_IM_LOWBAT
Low Battery Voltage Interrupt Mask
2
3
HIB_IM_RTCALT0
RTC Alert 0 Interrupt Mask
0
1
HIB_IM_RTCALT1
RTC Alert 1 Interrupt Mask
1
2
MIS
Hibernation Masked Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
HIB_MIS_EXTW
External Wake-Up Masked Interrupt Status
3
4
HIB_MIS_LOWBAT
Low Battery Voltage Masked Interrupt Status
2
3
HIB_MIS_RTCALT0
RTC Alert 0 Masked Interrupt Status
0
1
HIB_MIS_RTCALT1
RTC Alert 1 Masked Interrupt Status
1
2
RIS
Hibernation Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
HIB_RIS_EXTW
External Wake-Up Raw Interrupt Status
3
4
HIB_RIS_LOWBAT
Low Battery Voltage Raw Interrupt Status
2
3
HIB_RIS_RTCALT0
RTC Alert 0 Raw Interrupt Status
0
1
HIB_RIS_RTCALT1
RTC Alert 1 Raw Interrupt Status
1
2
RTCC
Hibernation RTC Counter
0x0
-1
read-write
n
0x0
0x0
HIB_RTCC
RTC Counter
0
32
RTCLD
Hibernation RTC Load
0xC
-1
read-write
n
0x0
0x0
HIB_RTCLD
RTC Load
0
32
RTCM0
Hibernation RTC Match 0
0x4
-1
read-write
n
0x0
0x0
HIB_RTCM0
RTC Match 0
0
32
RTCM1
Hibernation RTC Match 1
0x8
-1
read-write
n
0x0
0x0
HIB_RTCM1
RTC Match 1
0
32
RTCT
Hibernation RTC Trim
0x24
-1
read-write
n
0x0
0x0
HIB_RTCT_TRIM
RTC Trim Value
0
16
I2C0
Register map for I2C0 peripheral
I2C
0x0
0x0
0x1000
registers
n
I2C0MCR
I2C Master Configuration
0x20
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
I2C0MCS
I2C Master Control/Status
0x4
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C0MDR
I2C Master Data
0x8
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
I2C0MICR
I2C Master Interrupt Clear
0x1C
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
I2C0MIMR
I2C Master Interrupt Mask
0x10
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
I2C0MMIS
I2C Master Masked Interrupt Status
0x18
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
I2C0MRIS
I2C Master Raw Interrupt Status
0x14
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
I2C0MSA
I2C Master Slave Address
0x0
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
I2C0MTPR
I2C Master Timer Period
0xC
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
I2C0SCSR
I2C Slave Control/Status
0x804
read-write
n
0x0
0x0
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
I2C0SDR
I2C Slave Data
0x808
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
I2C0SICR
I2C Slave Interrupt Clear
0x818
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
I2C_SICR_STARTIC
Start Condition Interrupt Clear
1
2
write-only
I2C_SICR_STOPIC
Stop Condition Interrupt Clear
2
3
write-only
I2C0SIMR
I2C Slave Interrupt Mask
0x80C
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
I2C_SIMR_STARTIM
Start Condition Interrupt Mask
1
2
I2C_SIMR_STOPIM
Stop Condition Interrupt Mask
2
3
I2C0SMIS
I2C Slave Masked Interrupt Status
0x814
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
I2C_SMIS_STARTMIS
Start Condition Masked Interrupt Status
1
2
I2C_SMIS_STOPMIS
Stop Condition Masked Interrupt Status
2
3
I2C0SOAR
I2C Slave Own Address
0x800
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
I2C0SRIS
I2C Slave Raw Interrupt Status
0x810
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
I2C_SRIS_STARTRIS
Start Condition Raw Interrupt Status
1
2
I2C_SRIS_STOPRIS
Stop Condition Raw Interrupt Status
2
3
MCR
I2C Master Configuration
0x20
-1
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
MCS
I2C Master Control/Status
0x4
-1
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_BUSY
I2C Busy
0
1
I2C_MCS_DATACK
Acknowledge Data
3
4
I2C_MCS_ERROR
Error
1
2
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C_MCS_STOP
Generate STOP
2
3
MDR
I2C Master Data
0x8
-1
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
MICR
I2C Master Interrupt Clear
0x1C
-1
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
MIMR
I2C Master Interrupt Mask
0x10
-1
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
MMIS
I2C Master Masked Interrupt Status
0x18
-1
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
MRIS
I2C Master Raw Interrupt Status
0x14
-1
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
MSA
I2C Master Slave Address
0x0
-1
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
MTPR
I2C Master Timer Period
0xC
-1
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
SCSR
I2C Slave Control/Status
0x804
-1
read-write
n
0x0
0x0
I2C_SCSR_DA
Device Active
0
1
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
SDR
I2C Slave Data
0x808
-1
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
SICR
I2C Slave Interrupt Clear
0x818
-1
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
I2C_SICR_STARTIC
Start Condition Interrupt Clear
1
2
write-only
I2C_SICR_STOPIC
Stop Condition Interrupt Clear
2
3
write-only
SIMR
I2C Slave Interrupt Mask
0x80C
-1
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
I2C_SIMR_STARTIM
Start Condition Interrupt Mask
1
2
I2C_SIMR_STOPIM
Stop Condition Interrupt Mask
2
3
SMIS
I2C Slave Masked Interrupt Status
0x814
-1
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
I2C_SMIS_STARTMIS
Start Condition Masked Interrupt Status
1
2
I2C_SMIS_STOPMIS
Stop Condition Masked Interrupt Status
2
3
SOAR
I2C Slave Own Address
0x800
-1
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
SRIS
I2C Slave Raw Interrupt Status
0x810
-1
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
I2C_SRIS_STARTRIS
Start Condition Raw Interrupt Status
1
2
I2C_SRIS_STOPRIS
Stop Condition Raw Interrupt Status
2
3
I2C1
Register map for I2C0 peripheral
I2C
0x0
0x0
0x1000
registers
n
I2C0MCR
I2C Master Configuration
0x20
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
I2C0MCS
I2C Master Control/Status
0x4
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C0MDR
I2C Master Data
0x8
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
I2C0MICR
I2C Master Interrupt Clear
0x1C
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
I2C0MIMR
I2C Master Interrupt Mask
0x10
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
I2C0MMIS
I2C Master Masked Interrupt Status
0x18
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
I2C0MRIS
I2C Master Raw Interrupt Status
0x14
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
I2C0MSA
I2C Master Slave Address
0x0
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
I2C0MTPR
I2C Master Timer Period
0xC
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
I2C0SCSR
I2C Slave Control/Status
0x804
read-write
n
0x0
0x0
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
I2C0SDR
I2C Slave Data
0x808
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
I2C0SICR
I2C Slave Interrupt Clear
0x818
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
I2C_SICR_STARTIC
Start Condition Interrupt Clear
1
2
write-only
I2C_SICR_STOPIC
Stop Condition Interrupt Clear
2
3
write-only
I2C0SIMR
I2C Slave Interrupt Mask
0x80C
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
I2C_SIMR_STARTIM
Start Condition Interrupt Mask
1
2
I2C_SIMR_STOPIM
Stop Condition Interrupt Mask
2
3
I2C0SMIS
I2C Slave Masked Interrupt Status
0x814
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
I2C_SMIS_STARTMIS
Start Condition Masked Interrupt Status
1
2
I2C_SMIS_STOPMIS
Stop Condition Masked Interrupt Status
2
3
I2C0SOAR
I2C Slave Own Address
0x800
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
I2C0SRIS
I2C Slave Raw Interrupt Status
0x810
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
I2C_SRIS_STARTRIS
Start Condition Raw Interrupt Status
1
2
I2C_SRIS_STOPRIS
Stop Condition Raw Interrupt Status
2
3
MCR
I2C Master Configuration
0x20
-1
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
MCS
I2C Master Control/Status
0x4
-1
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_BUSY
I2C Busy
0
1
I2C_MCS_DATACK
Acknowledge Data
3
4
I2C_MCS_ERROR
Error
1
2
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C_MCS_STOP
Generate STOP
2
3
MDR
I2C Master Data
0x8
-1
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
MICR
I2C Master Interrupt Clear
0x1C
-1
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
MIMR
I2C Master Interrupt Mask
0x10
-1
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
MMIS
I2C Master Masked Interrupt Status
0x18
-1
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
MRIS
I2C Master Raw Interrupt Status
0x14
-1
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
MSA
I2C Master Slave Address
0x0
-1
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
MTPR
I2C Master Timer Period
0xC
-1
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
SCSR
I2C Slave Control/Status
0x804
-1
read-write
n
0x0
0x0
I2C_SCSR_DA
Device Active
0
1
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
SDR
I2C Slave Data
0x808
-1
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
SICR
I2C Slave Interrupt Clear
0x818
-1
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
I2C_SICR_STARTIC
Start Condition Interrupt Clear
1
2
write-only
I2C_SICR_STOPIC
Stop Condition Interrupt Clear
2
3
write-only
SIMR
I2C Slave Interrupt Mask
0x80C
-1
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
I2C_SIMR_STARTIM
Start Condition Interrupt Mask
1
2
I2C_SIMR_STOPIM
Stop Condition Interrupt Mask
2
3
SMIS
I2C Slave Masked Interrupt Status
0x814
-1
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
I2C_SMIS_STARTMIS
Start Condition Masked Interrupt Status
1
2
I2C_SMIS_STOPMIS
Stop Condition Masked Interrupt Status
2
3
SOAR
I2C Slave Own Address
0x800
-1
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
SRIS
I2C Slave Raw Interrupt Status
0x810
-1
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
I2C_SRIS_STARTRIS
Start Condition Raw Interrupt Status
1
2
I2C_SRIS_STOPRIS
Stop Condition Raw Interrupt Status
2
3
I2S0
Register map for I2S0 peripheral
I2S
0x0
0x0
0x1000
registers
n
CFG
I2S Module Configuration
0xC00
-1
read-write
n
0x0
0x0
I2S_CFG_RXEN
Serial Receive Engine Enable
1
2
I2S_CFG_RXSLV
Use External I2S0RXMCLK
5
6
I2S_CFG_TXEN
Serial Transmit Engine Enable
0
1
I2S_CFG_TXSLV
Use External I2S0TXMCLK
4
5
I2S0CFG
I2S Module Configuration
0xC00
read-write
n
0x0
0x0
I2S_CFG_RXEN
Serial Receive Engine Enable
1
2
I2S_CFG_RXSLV
Use External I2S0RXMCLK
5
6
I2S_CFG_TXEN
Serial Transmit Engine Enable
0
1
I2S_CFG_TXSLV
Use External I2S0TXMCLK
4
5
I2S0IC
I2S Interrupt Clear
0xC1C
write-only
n
0x0
0x0
I2S_IC_RXRE
Receive FIFO Read Error
5
6
write-only
I2S_IC_TXWE
Transmit FIFO Write Error
1
2
write-only
I2S0IM
I2S Interrupt Mask
0xC10
read-write
n
0x0
0x0
I2S_IM_RXFSR
Receive FIFO Service Request
4
5
I2S_IM_RXRE
Receive FIFO Read Error
5
6
I2S_IM_TXFSR
Transmit FIFO Service Request
0
1
I2S_IM_TXWE
Transmit FIFO Write Error
1
2
I2S0MIS
I2S Masked Interrupt Status
0xC18
read-write
n
0x0
0x0
I2S_MIS_RXFSR
Receive FIFO Service Request
4
5
I2S_MIS_RXRE
Receive FIFO Read Error
5
6
I2S_MIS_TXFSR
Transmit FIFO Service Request
0
1
I2S_MIS_TXWE
Transmit FIFO Write Error
1
2
I2S0RIS
I2S Raw Interrupt Status
0xC14
read-write
n
0x0
0x0
I2S_RIS_RXFSR
Receive FIFO Service Request
4
5
I2S_RIS_RXRE
Receive FIFO Read Error
5
6
I2S_RIS_TXFSR
Transmit FIFO Service Request
0
1
I2S_RIS_TXWE
Transmit FIFO Write Error
1
2
I2S0RXCFG
I2S Receive Module Configuration
0x808
read-write
n
0x0
0x0
I2S_RXCFG_DLY
Data Delay
28
29
I2S_RXCFG_JST
Justification of Input Data
29
30
I2S_RXCFG_LRP
Left/Right Clock Polarity
26
27
I2S_RXCFG_MSL
SCLK Master/Slave
22
23
I2S_RXCFG_RM
Read Mode
24
25
I2S_RXCFG_SCP
SCLK Polarity
27
28
I2S_RXCFG_SDSZ
System Data Size
4
10
I2S_RXCFG_SSZ
Sample Size
10
16
I2S0RXFIFO
I2S Receive FIFO Data
0x800
read-write
n
0x0
0x0
I2S_RXFIFO
RX Data
0
32
I2S0RXFIFOCFG
I2S Receive FIFO Configuration
0x804
read-write
n
0x0
0x0
I2S_RXFIFOCFG_CSS
Compact Stereo Sample Size
1
2
I2S_RXFIFOCFG_FMM
FIFO Mono Mode
2
3
I2S_RXFIFOCFG_LRS
Left-Right Sample Indicator
0
1
I2S0RXISM
I2S Receive Interrupt Status and Mask
0x810
read-write
n
0x0
0x0
I2S_RXISM_FFI
Receive FIFO Service Request Interrupt
16
17
I2S_RXISM_FFM
FIFO Interrupt Mask
0
1
I2S0RXLEV
I2S Receive FIFO Level
0x818
read-write
n
0x0
0x0
I2S_RXLEV_LEVEL
Number of Audio Samples
0
5
I2S0RXLIMIT
I2S Receive FIFO Limit
0x80C
read-write
n
0x0
0x0
I2S_RXLIMIT_LIMIT
FIFO Limit
0
5
I2S0TXCFG
I2S Transmit Module Configuration
0x8
read-write
n
0x0
0x0
I2S_TXCFG_DLY
Data Delay
28
29
I2S_TXCFG_FMT
FIFO Empty
23
24
I2S_TXCFG_JST
Justification of Output Data
29
30
I2S_TXCFG_LRP
Left/Right Clock Polarity
26
27
I2S_TXCFG_MSL
SCLK Master/Slave
22
23
I2S_TXCFG_SCP
SCLK Polarity
27
28
I2S_TXCFG_SDSZ
System Data Size
4
10
I2S_TXCFG_SSZ
Sample Size
10
16
I2S_TXCFG_WM
Write Mode
24
26
I2S_TXCFG_WM_DUAL
Stereo mode
0x0
I2S_TXCFG_WM_COMPACT
Compact Stereo mode
0x1
I2S_TXCFG_WM_MONO
Mono mode
0x2
I2S0TXFIFO
I2S Transmit FIFO Data
0x0
write-only
n
0x0
0x0
I2S_TXFIFO
TX Data
0
32
write-only
I2S0TXFIFOCFG
I2S Transmit FIFO Configuration
0x4
read-write
n
0x0
0x0
I2S_TXFIFOCFG_CSS
Compact Stereo Sample Size
1
2
I2S_TXFIFOCFG_LRS
Left-Right Sample Indicator
0
1
I2S0TXISM
I2S Transmit Interrupt Status and Mask
0x10
read-write
n
0x0
0x0
I2S_TXISM_FFI
Transmit FIFO Service Request Interrupt
16
17
I2S_TXISM_FFM
FIFO Interrupt Mask
0
1
I2S0TXLEV
I2S Transmit FIFO Level
0x18
read-write
n
0x0
0x0
I2S_TXLEV_LEVEL
Number of Audio Samples
0
5
I2S0TXLIMIT
I2S Transmit FIFO Limit
0xC
read-write
n
0x0
0x0
I2S_TXLIMIT_LIMIT
FIFO Limit
0
5
IC
I2S Interrupt Clear
0xC1C
-1
write-only
n
0x0
0x0
I2S_IC_RXRE
Receive FIFO Read Error
5
6
write-only
I2S_IC_TXWE
Transmit FIFO Write Error
1
2
write-only
IM
I2S Interrupt Mask
0xC10
-1
read-write
n
0x0
0x0
I2S_IM_RXFSR
Receive FIFO Service Request
4
5
I2S_IM_RXRE
Receive FIFO Read Error
5
6
I2S_IM_TXFSR
Transmit FIFO Service Request
0
1
I2S_IM_TXWE
Transmit FIFO Write Error
1
2
MIS
I2S Masked Interrupt Status
0xC18
-1
read-write
n
0x0
0x0
I2S_MIS_RXFSR
Receive FIFO Service Request
4
5
I2S_MIS_RXRE
Receive FIFO Read Error
5
6
I2S_MIS_TXFSR
Transmit FIFO Service Request
0
1
I2S_MIS_TXWE
Transmit FIFO Write Error
1
2
RIS
I2S Raw Interrupt Status
0xC14
-1
read-write
n
0x0
0x0
I2S_RIS_RXFSR
Receive FIFO Service Request
4
5
I2S_RIS_RXRE
Receive FIFO Read Error
5
6
I2S_RIS_TXFSR
Transmit FIFO Service Request
0
1
I2S_RIS_TXWE
Transmit FIFO Write Error
1
2
RXCFG
I2S Receive Module Configuration
0x808
-1
read-write
n
0x0
0x0
I2S_RXCFG_DLY
Data Delay
28
29
I2S_RXCFG_JST
Justification of Input Data
29
30
I2S_RXCFG_LRP
Left/Right Clock Polarity
26
27
I2S_RXCFG_MSL
SCLK Master/Slave
22
23
I2S_RXCFG_RM
Read Mode
24
25
I2S_RXCFG_SCP
SCLK Polarity
27
28
I2S_RXCFG_SDSZ
System Data Size
4
10
I2S_RXCFG_SSZ
Sample Size
10
16
RXFIFO
I2S Receive FIFO Data
0x800
-1
read-write
n
0x0
0x0
I2S_RXFIFO
RX Data
0
32
RXFIFOCFG
I2S Receive FIFO Configuration
0x804
-1
read-write
n
0x0
0x0
I2S_RXFIFOCFG_CSS
Compact Stereo Sample Size
1
2
I2S_RXFIFOCFG_FMM
FIFO Mono Mode
2
3
I2S_RXFIFOCFG_LRS
Left-Right Sample Indicator
0
1
RXISM
I2S Receive Interrupt Status and Mask
0x810
-1
read-write
n
0x0
0x0
I2S_RXISM_FFI
Receive FIFO Service Request Interrupt
16
17
I2S_RXISM_FFM
FIFO Interrupt Mask
0
1
RXLEV
I2S Receive FIFO Level
0x818
-1
read-write
n
0x0
0x0
I2S_RXLEV_LEVEL
Number of Audio Samples
0
5
RXLIMIT
I2S Receive FIFO Limit
0x80C
-1
read-write
n
0x0
0x0
I2S_RXLIMIT_LIMIT
FIFO Limit
0
5
TXCFG
I2S Transmit Module Configuration
0x8
-1
read-write
n
0x0
0x0
I2S_TXCFG_DLY
Data Delay
28
29
I2S_TXCFG_FMT
FIFO Empty
23
24
I2S_TXCFG_JST
Justification of Output Data
29
30
I2S_TXCFG_LRP
Left/Right Clock Polarity
26
27
I2S_TXCFG_MSL
SCLK Master/Slave
22
23
I2S_TXCFG_SCP
SCLK Polarity
27
28
I2S_TXCFG_SDSZ
System Data Size
4
10
I2S_TXCFG_SSZ
Sample Size
10
16
I2S_TXCFG_WM
Write Mode
24
26
I2S_TXCFG_WM_DUAL
Stereo mode
0x0
I2S_TXCFG_WM_COMPACT
Compact Stereo mode
0x1
I2S_TXCFG_WM_MONO
Mono mode
0x2
TXFIFO
I2S Transmit FIFO Data
0x0
-1
write-only
n
0x0
0x0
I2S_TXFIFO
TX Data
0
32
write-only
TXFIFOCFG
I2S Transmit FIFO Configuration
0x4
-1
read-write
n
0x0
0x0
I2S_TXFIFOCFG_CSS
Compact Stereo Sample Size
1
2
I2S_TXFIFOCFG_LRS
Left-Right Sample Indicator
0
1
TXISM
I2S Transmit Interrupt Status and Mask
0x10
-1
read-write
n
0x0
0x0
I2S_TXISM_FFI
Transmit FIFO Service Request Interrupt
16
17
I2S_TXISM_FFM
FIFO Interrupt Mask
0
1
TXLEV
I2S Transmit FIFO Level
0x18
-1
read-write
n
0x0
0x0
I2S_TXLEV_LEVEL
Number of Audio Samples
0
5
TXLIMIT
I2S Transmit FIFO Limit
0xC
-1
read-write
n
0x0
0x0
I2S_TXLIMIT_LIMIT
FIFO Limit
0
5
MAC
Register map for MAC peripheral
MAC
0x0
0x0
0x1000
registers
n
DATA
Ethernet MAC Data
0x10
-1
read-write
n
0x0
0x0
MAC_DATA_RXDATA
Receive FIFO Data
0
32
MAC_DATA_TXDATA
Transmit FIFO Data
0
32
IA0
Ethernet MAC Individual Address 0
0x14
-1
read-write
n
0x0
0x0
MAC_IA0_MACOCT1
MAC Address Octet 1
0
8
MAC_IA0_MACOCT2
MAC Address Octet 2
8
16
MAC_IA0_MACOCT3
MAC Address Octet 3
16
24
MAC_IA0_MACOCT4
MAC Address Octet 4
24
32
IA1
Ethernet MAC Individual Address 1
0x18
-1
read-write
n
0x0
0x0
MAC_IA1_MACOCT5
MAC Address Octet 5
0
8
MAC_IA1_MACOCT6
MAC Address Octet 6
8
16
IM
Ethernet MAC Interrupt Mask
0x4
-1
read-write
n
0x0
0x0
MAC_IM_FOVM
Mask FIFO Overrun
3
4
MAC_IM_MDINTM
Mask MII Transaction Complete
5
6
MAC_IM_PHYINTM
Mask PHY Interrupt
6
7
MAC_IM_RXERM
Mask Receive Error
4
5
MAC_IM_RXINTM
Mask Packet Received
0
1
MAC_IM_TXEMPM
Mask Transmit FIFO Empty
2
3
MAC_IM_TXERM
Mask Transmit Error
1
2
LED
Ethernet MAC LED Encoding
0x40
-1
read-write
n
0x0
0x0
MAC_LED_LED0
LED0 Source
0
4
MAC_LED_LED0_LINK
Link OK (Default LED0)
0x0
MAC_LED_LED0_RXTX
RX or TX Activity
0x1
MAC_LED_LED0_100
100BASE-TX mode
0x5
MAC_LED_LED0_10
10BASE-T mode
0x6
MAC_LED_LED0_DUPLEX
Full-Duplex
0x7
MAC_LED_LED0_LINKACT
Link OK and Blink=RX or TX Activity
0x8
MAC_LED_LED1
LED1 Source
8
12
MAC_LED_LED1_LINK
Link OK
0x0
MAC_LED_LED1_RXTX
RX or TX Activity (Default LED1)
0x1
MAC_LED_LED1_100
100BASE-TX mode
0x5
MAC_LED_LED1_10
10BASE-T mode
0x6
MAC_LED_LED1_DUPLEX
Full-Duplex
0x7
MAC_LED_LED1_LINKACT
Link OK and Blink=RX or TX Activity
0x8
MACDATA
Ethernet MAC Data
0x10
read-write
n
0x0
0x0
MAC_DATA_RXDATA
Receive FIFO Data
0
32
MACIA0
Ethernet MAC Individual Address 0
0x14
read-write
n
0x0
0x0
MAC_IA0_MACOCT1
MAC Address Octet 1
0
8
MAC_IA0_MACOCT2
MAC Address Octet 2
8
16
MAC_IA0_MACOCT3
MAC Address Octet 3
16
24
MAC_IA0_MACOCT4
MAC Address Octet 4
24
32
MACIA1
Ethernet MAC Individual Address 1
0x18
read-write
n
0x0
0x0
MAC_IA1_MACOCT5
MAC Address Octet 5
0
8
MAC_IA1_MACOCT6
MAC Address Octet 6
8
16
MACIM
Ethernet MAC Interrupt Mask
0x4
read-write
n
0x0
0x0
MAC_IM_FOVM
Mask FIFO Overrun
3
4
MAC_IM_MDINTM
Mask MII Transaction Complete
5
6
MAC_IM_PHYINTM
Mask PHY Interrupt
6
7
MAC_IM_RXERM
Mask Receive Error
4
5
MAC_IM_RXINTM
Mask Packet Received
0
1
MAC_IM_TXEMPM
Mask Transmit FIFO Empty
2
3
MAC_IM_TXERM
Mask Transmit Error
1
2
MACLED
Ethernet MAC LED Encoding
0x40
read-write
n
0x0
0x0
MAC_LED_LED0
LED0 Source
0
4
MAC_LED_LED0_LINK
Link OK (Default LED0)
0x0
MAC_LED_LED0_RXTX
RX or TX Activity
0x1
MAC_LED_LED0_100
100BASE-TX mode
0x5
MAC_LED_LED0_10
10BASE-T mode
0x6
MAC_LED_LED0_DUPLEX
Full-Duplex
0x7
MAC_LED_LED0_LINKACT
Link OK & Blink=RX or TX Activity
0x8
MAC_LED_LED1
LED1 Source
8
12
MAC_LED_LED1_LINK
Link OK
0x0
MAC_LED_LED1_RXTX
RX or TX Activity (Default LED1)
0x1
MAC_LED_LED1_100
100BASE-TX mode
0x5
MAC_LED_LED1_10
10BASE-T mode
0x6
MAC_LED_LED1_DUPLEX
Full-Duplex
0x7
MAC_LED_LED1_LINKACT
Link OK & Blink=RX or TX Activity
0x8
MACMCTL
Ethernet MAC Management Control
0x20
read-write
n
0x0
0x0
MAC_MCTL_REGADR
MII Register Address
3
8
MAC_MCTL_START
MII Register Transaction Enable
0
1
MAC_MCTL_WRITE
MII Register Transaction Type
1
2
MACMDIX
Ethernet PHY MDIX
0x44
read-write
n
0x0
0x0
MAC_MDIX_EN
MDI/MDI-X Enable
0
1
MACMDV
Ethernet MAC Management Divider
0x24
read-write
n
0x0
0x0
MAC_MDV_DIV
Clock Divider
0
8
MACMRXD
Ethernet MAC Management Receive Data
0x30
read-write
n
0x0
0x0
MAC_MRXD_MDRX
MII Register Receive Data
0
16
MACMTXD
Ethernet MAC Management Transmit Data
0x2C
read-write
n
0x0
0x0
MAC_MTXD_MDTX
MII Register Transmit Data
0
16
MACNP
Ethernet MAC Number of Packets
0x34
read-write
n
0x0
0x0
MAC_NP_NPR
Number of Packets in Receive FIFO
0
6
MACRCTL
Ethernet MAC Receive Control
0x8
read-write
n
0x0
0x0
MAC_RCTL_AMUL
Enable Multicast Frames
1
2
MAC_RCTL_BADCRC
Enable Reject Bad CRC
3
4
MAC_RCTL_PRMS
Enable Promiscuous Mode
2
3
MAC_RCTL_RSTFIFO
Clear Receive FIFO
4
5
MAC_RCTL_RXEN
Enable Receiver
0
1
MACRIS
Ethernet MAC Raw Interrupt Status/Acknowledge
0x0
read-write
n
0x0
0x0
MAC_RIS_FOV
FIFO Overrun
3
4
MAC_RIS_MDINT
MII Transaction Complete
5
6
MAC_RIS_PHYINT
PHY Interrupt
6
7
MAC_RIS_RXER
Receive Error
4
5
MAC_RIS_RXINT
Packet Received
0
1
MAC_RIS_TXEMP
Transmit FIFO Empty
2
3
MAC_RIS_TXER
Transmit Error
1
2
MACTCTL
Ethernet MAC Transmit Control
0xC
read-write
n
0x0
0x0
MAC_TCTL_CRC
Enable CRC Generation
2
3
MAC_TCTL_DUPLEX
Enable Duplex Mode
4
5
MAC_TCTL_PADEN
Enable Packet Padding
1
2
MAC_TCTL_TXEN
Enable Transmitter
0
1
MACTHR
Ethernet MAC Threshold
0x1C
read-write
n
0x0
0x0
MAC_THR_THRESH
Threshold Value
0
6
MACTR
Ethernet MAC Transmission Request
0x38
read-write
n
0x0
0x0
MAC_TR_NEWTX
New Transmission
0
1
MACTS
Ethernet MAC Timer Support
0x3C
read-write
n
0x0
0x0
MAC_TS_TSEN
Time Stamp Enable
0
1
MCTL
Ethernet MAC Management Control
0x20
-1
read-write
n
0x0
0x0
MAC_MCTL_REGADR
MII Register Address
3
8
MAC_MCTL_START
MII Register Transaction Enable
0
1
MAC_MCTL_WRITE
MII Register Transaction Type
1
2
MDIX
Ethernet PHY MDIX
0x44
-1
read-write
n
0x0
0x0
MAC_MDIX_EN
MDI/MDI-X Enable
0
1
MDV
Ethernet MAC Management Divider
0x24
-1
read-write
n
0x0
0x0
MAC_MDV_DIV
Clock Divider
0
8
MRXD
Ethernet MAC Management Receive Data
0x30
-1
read-write
n
0x0
0x0
MAC_MRXD_MDRX
MII Register Receive Data
0
16
MTXD
Ethernet MAC Management Transmit Data
0x2C
-1
read-write
n
0x0
0x0
MAC_MTXD_MDTX
MII Register Transmit Data
0
16
NP
Ethernet MAC Number of Packets
0x34
-1
read-write
n
0x0
0x0
MAC_NP_NPR
Number of Packets in Receive FIFO
0
6
RCTL
Ethernet MAC Receive Control
0x8
-1
read-write
n
0x0
0x0
MAC_RCTL_AMUL
Enable Multicast Frames
1
2
MAC_RCTL_BADCRC
Enable Reject Bad CRC
3
4
MAC_RCTL_PRMS
Enable Promiscuous Mode
2
3
MAC_RCTL_RSTFIFO
Clear Receive FIFO
4
5
MAC_RCTL_RXEN
Enable Receiver
0
1
RIS
Ethernet MAC Raw Interrupt Status/Acknowledge
0x0
-1
read-write
n
0x0
0x0
MAC_RIS_FOV
FIFO Overrun
3
4
MAC_RIS_MDINT
MII Transaction Complete
5
6
MAC_RIS_PHYINT
PHY Interrupt
6
7
MAC_RIS_RXER
Receive Error
4
5
MAC_RIS_RXINT
Packet Received
0
1
MAC_RIS_TXEMP
Transmit FIFO Empty
2
3
MAC_RIS_TXER
Transmit Error
1
2
TCTL
Ethernet MAC Transmit Control
0xC
-1
read-write
n
0x0
0x0
MAC_TCTL_CRC
Enable CRC Generation
2
3
MAC_TCTL_DUPLEX
Enable Duplex Mode
4
5
MAC_TCTL_PADEN
Enable Packet Padding
1
2
MAC_TCTL_TXEN
Enable Transmitter
0
1
THR
Ethernet MAC Threshold
0x1C
-1
read-write
n
0x0
0x0
MAC_THR_THRESH
Threshold Value
0
6
TR
Ethernet MAC Transmission Request
0x38
-1
read-write
n
0x0
0x0
MAC_TR_NEWTX
New Transmission
0
1
TS
Ethernet MAC Timer Support
0x3C
-1
read-write
n
0x0
0x0
MAC_TS_TSEN
Time Stamp Enable
0
1
NVIC
Register map for NVIC peripheral
NVIC
0x0
0x0
0x1000
registers
n
ACTIVE0
Interrupt 0-31 Active Bit
0x300
-1
read-write
n
0x0
0x0
NVIC_ACTIVE0_INT
Interrupt Active
0
32
NVIC_ACTIVE0_INT0
Interrupt 0 active
0x1
NVIC_ACTIVE0_INT4
Interrupt 4 active
0x10
NVIC_ACTIVE0_INT8
Interrupt 8 active
0x100
NVIC_ACTIVE0_INT12
Interrupt 12 active
0x1000
NVIC_ACTIVE0_INT16
Interrupt 16 active
0x10000
NVIC_ACTIVE0_INT20
Interrupt 20 active
0x100000
NVIC_ACTIVE0_INT24
Interrupt 24 active
0x1000000
NVIC_ACTIVE0_INT28
Interrupt 28 active
0x10000000
NVIC_ACTIVE0_INT1
Interrupt 1 active
0x2
NVIC_ACTIVE0_INT5
Interrupt 5 active
0x20
NVIC_ACTIVE0_INT9
Interrupt 9 active
0x200
NVIC_ACTIVE0_INT13
Interrupt 13 active
0x2000
NVIC_ACTIVE0_INT17
Interrupt 17 active
0x20000
NVIC_ACTIVE0_INT21
Interrupt 21 active
0x200000
NVIC_ACTIVE0_INT25
Interrupt 25 active
0x2000000
NVIC_ACTIVE0_INT29
Interrupt 29 active
0x20000000
NVIC_ACTIVE0_INT2
Interrupt 2 active
0x4
NVIC_ACTIVE0_INT6
Interrupt 6 active
0x40
NVIC_ACTIVE0_INT10
Interrupt 10 active
0x400
NVIC_ACTIVE0_INT14
Interrupt 14 active
0x4000
NVIC_ACTIVE0_INT18
Interrupt 18 active
0x40000
NVIC_ACTIVE0_INT22
Interrupt 22 active
0x400000
NVIC_ACTIVE0_INT26
Interrupt 26 active
0x4000000
NVIC_ACTIVE0_INT30
Interrupt 30 active
0x40000000
NVIC_ACTIVE0_INT3
Interrupt 3 active
0x8
NVIC_ACTIVE0_INT7
Interrupt 7 active
0x80
NVIC_ACTIVE0_INT11
Interrupt 11 active
0x800
NVIC_ACTIVE0_INT15
Interrupt 15 active
0x8000
NVIC_ACTIVE0_INT19
Interrupt 19 active
0x80000
NVIC_ACTIVE0_INT23
Interrupt 23 active
0x800000
NVIC_ACTIVE0_INT27
Interrupt 27 active
0x8000000
NVIC_ACTIVE0_INT31
Interrupt 31 active
0x80000000
ACTIVE1
Interrupt 32-54 Active Bit
0x304
-1
read-write
n
0x0
0x0
NVIC_ACTIVE1_INT
Interrupt Active
0
23
NVIC_ACTIVE1_INT32
Interrupt 32 active
0x1
NVIC_ACTIVE1_INT36
Interrupt 36 active
0x10
NVIC_ACTIVE1_INT40
Interrupt 40 active
0x100
NVIC_ACTIVE1_INT44
Interrupt 44 active
0x1000
NVIC_ACTIVE1_INT48
Interrupt 48 active
0x10000
NVIC_ACTIVE1_INT52
Interrupt 52 active
0x100000
NVIC_ACTIVE1_INT33
Interrupt 33 active
0x2
NVIC_ACTIVE1_INT37
Interrupt 37 active
0x20
NVIC_ACTIVE1_INT41
Interrupt 41 active
0x200
NVIC_ACTIVE1_INT45
Interrupt 45 active
0x2000
NVIC_ACTIVE1_INT49
Interrupt 49 active
0x20000
NVIC_ACTIVE1_INT53
Interrupt 53 active
0x200000
NVIC_ACTIVE1_INT34
Interrupt 34 active
0x4
NVIC_ACTIVE1_INT38
Interrupt 38 active
0x40
NVIC_ACTIVE1_INT42
Interrupt 42 active
0x400
NVIC_ACTIVE1_INT46
Interrupt 46 active
0x4000
NVIC_ACTIVE1_INT50
Interrupt 50 active
0x40000
NVIC_ACTIVE1_INT54
Interrupt 54 active
0x400000
NVIC_ACTIVE1_INT35
Interrupt 35 active
0x8
NVIC_ACTIVE1_INT39
Interrupt 39 active
0x80
NVIC_ACTIVE1_INT43
Interrupt 43 active
0x800
NVIC_ACTIVE1_INT47
Interrupt 47 active
0x8000
NVIC_ACTIVE1_INT51
Interrupt 51 active
0x80000
ACTLR
Auxiliary Control
0x8
-1
read-write
n
0x0
0x0
NVIC_ACTLR_DISFOLD
Disable IT Folding
2
3
NVIC_ACTLR_DISMCYC
Disable Interrupts of Multiple Cycle Instructions
0
1
NVIC_ACTLR_DISWBUF
Disable Write Buffer
1
2
APINT
Application Interrupt and Reset Control
0xD0C
-1
read-write
n
0x0
0x0
NVIC_APINT_ENDIANESS
Data Endianess
15
16
NVIC_APINT_PRIGROUP
Interrupt Priority Grouping
8
11
NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x0
NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x1
NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x2
NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x3
NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x4
NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x5
NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x6
NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
0x7
NVIC_APINT_SYSRESETREQ
System Reset Request
2
3
NVIC_APINT_VECTKEY
Register Key
16
32
NVIC_APINT_VECTKEY
Vector key
0x5fa
NVIC_APINT_VECT_CLR_ACT
Clear Active NMI / Fault
1
2
NVIC_APINT_VECT_RESET
System Reset
0
1
CFG_CTRL
Configuration and Control
0xD14
-1
read-write
n
0x0
0x0
NVIC_CFG_CTRL_BASE_THR
Thread State Control
0
1
NVIC_CFG_CTRL_BFHFNMIGN
Ignore Bus Fault in NMI and Fault
8
9
NVIC_CFG_CTRL_DIV0
Trap on Divide by 0
4
5
NVIC_CFG_CTRL_MAIN_PEND
Allow Main Interrupt Trigger
1
2
NVIC_CFG_CTRL_STKALIGN
Stack Alignment on Exception Entry
9
10
NVIC_CFG_CTRL_UNALIGNED
Trap on Unaligned Access
3
4
CPUID
CPU ID Base
0xD00
-1
read-write
n
0x0
0x0
NVIC_CPUID_CON
Constant
16
20
NVIC_CPUID_IMP
Implementer Code
24
32
NVIC_CPUID_IMP_ARM
ARM
0x41
NVIC_CPUID_PARTNO
Part Number
4
16
NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
0xc23
NVIC_CPUID_REV
Revision Number
0
4
NVIC_CPUID_VAR
Variant Number
20
24
DBG_CTRL
Debug Control and Status Reg
0xDF0
-1
read-write
n
0x0
0x0
NVIC_DBG_CTRL_C_DEBUGEN
Enable debug
0
1
NVIC_DBG_CTRL_C_HALT
Halt the core
1
2
NVIC_DBG_CTRL_C_MASKINT
Mask interrupts when stepping
3
4
NVIC_DBG_CTRL_C_SNAPSTALL
Breaks a stalled load/store
5
6
NVIC_DBG_CTRL_C_STEP
Step the core
2
3
NVIC_DBG_CTRL_S_HALT
Core status on halt
17
18
NVIC_DBG_CTRL_S_LOCKUP
Core is locked up
19
20
NVIC_DBG_CTRL_S_REGRDY
Register read/write available
16
17
NVIC_DBG_CTRL_S_RESET_ST
Core has reset since last read
25
26
NVIC_DBG_CTRL_S_RETIRE_ST
Core has executed insruction since last read
24
25
NVIC_DBG_CTRL_S_SLEEP
Core is sleeping
18
19
DBG_DATA
Debug Core Register Data
0xDF8
-1
read-write
n
0x0
0x0
NVIC_DBG_DATA
Data temporary cache
0
32
DBG_INT
Debug Reset Interrupt Control
0xDFC
-1
read-write
n
0x0
0x0
NVIC_DBG_INT_BUSERR
Debug trap on bus error
8
9
NVIC_DBG_INT_CHKERR
Debug trap on usage fault check
6
7
NVIC_DBG_INT_HARDERR
Debug trap on hard fault
10
11
NVIC_DBG_INT_INTERR
Debug trap on interrupt errors
9
10
NVIC_DBG_INT_MMERR
Debug trap on mem manage fault
4
5
NVIC_DBG_INT_NOCPERR
Debug trap on coprocessor error
5
6
NVIC_DBG_INT_RESET
Core reset status
3
4
NVIC_DBG_INT_RSTPENDCLR
Clear pending core reset
2
3
NVIC_DBG_INT_RSTPENDING
Core reset is pending
1
2
NVIC_DBG_INT_RSTVCATCH
Reset vector catch
0
1
NVIC_DBG_INT_STATERR
Debug trap on usage fault state
7
8
DBG_XFER
Debug Core Reg. Transfer Select
0xDF4
-1
read-write
n
0x0
0x0
NVIC_DBG_XFER_REG_SEL
Register
0
5
NVIC_DBG_XFER_REG_R0
Register R0
0x0
NVIC_DBG_XFER_REG_R1
Register R1
0x1
NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x10
NVIC_DBG_XFER_REG_MSP
Main SP
0x11
NVIC_DBG_XFER_REG_PSP
Process SP
0x12
NVIC_DBG_XFER_REG_DSP
Deep SP
0x13
NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
0x14
NVIC_DBG_XFER_REG_R2
Register R2
0x2
NVIC_DBG_XFER_REG_R3
Register R3
0x3
NVIC_DBG_XFER_REG_R4
Register R4
0x4
NVIC_DBG_XFER_REG_R5
Register R5
0x5
NVIC_DBG_XFER_REG_R6
Register R6
0x6
NVIC_DBG_XFER_REG_R7
Register R7
0x7
NVIC_DBG_XFER_REG_R8
Register R8
0x8
NVIC_DBG_XFER_REG_R9
Register R9
0x9
NVIC_DBG_XFER_REG_R10
Register R10
0xa
NVIC_DBG_XFER_REG_R11
Register R11
0xb
NVIC_DBG_XFER_REG_R12
Register R12
0xc
NVIC_DBG_XFER_REG_R13
Register R13
0xd
NVIC_DBG_XFER_REG_R14
Register R14
0xe
NVIC_DBG_XFER_REG_R15
Register R15
0xf
NVIC_DBG_XFER_REG_WNR
Write or not read
16
17
DEBUG_STAT
Debug Status Register
0xD30
-1
read-write
n
0x0
0x0
NVIC_DEBUG_STAT_BKPT
Breakpoint instruction
1
2
NVIC_DEBUG_STAT_DWTTRAP
DWT match
2
3
NVIC_DEBUG_STAT_EXTRNL
EDBGRQ asserted
4
5
NVIC_DEBUG_STAT_HALTED
Halt request
0
1
NVIC_DEBUG_STAT_VCATCH
Vector catch
3
4
DIS0
Interrupt 0-31 Clear Enable
0x180
-1
read-write
n
0x0
0x0
NVIC_DIS0_INT
Interrupt Disable
0
32
NVIC_DIS0_INT0
Interrupt 0 disable
0x1
NVIC_DIS0_INT4
Interrupt 4 disable
0x10
NVIC_DIS0_INT8
Interrupt 8 disable
0x100
NVIC_DIS0_INT12
Interrupt 12 disable
0x1000
NVIC_DIS0_INT16
Interrupt 16 disable
0x10000
NVIC_DIS0_INT20
Interrupt 20 disable
0x100000
NVIC_DIS0_INT24
Interrupt 24 disable
0x1000000
NVIC_DIS0_INT28
Interrupt 28 disable
0x10000000
NVIC_DIS0_INT1
Interrupt 1 disable
0x2
NVIC_DIS0_INT5
Interrupt 5 disable
0x20
NVIC_DIS0_INT9
Interrupt 9 disable
0x200
NVIC_DIS0_INT13
Interrupt 13 disable
0x2000
NVIC_DIS0_INT17
Interrupt 17 disable
0x20000
NVIC_DIS0_INT21
Interrupt 21 disable
0x200000
NVIC_DIS0_INT25
Interrupt 25 disable
0x2000000
NVIC_DIS0_INT29
Interrupt 29 disable
0x20000000
NVIC_DIS0_INT2
Interrupt 2 disable
0x4
NVIC_DIS0_INT6
Interrupt 6 disable
0x40
NVIC_DIS0_INT10
Interrupt 10 disable
0x400
NVIC_DIS0_INT14
Interrupt 14 disable
0x4000
NVIC_DIS0_INT18
Interrupt 18 disable
0x40000
NVIC_DIS0_INT22
Interrupt 22 disable
0x400000
NVIC_DIS0_INT26
Interrupt 26 disable
0x4000000
NVIC_DIS0_INT30
Interrupt 30 disable
0x40000000
NVIC_DIS0_INT3
Interrupt 3 disable
0x8
NVIC_DIS0_INT7
Interrupt 7 disable
0x80
NVIC_DIS0_INT11
Interrupt 11 disable
0x800
NVIC_DIS0_INT15
Interrupt 15 disable
0x8000
NVIC_DIS0_INT19
Interrupt 19 disable
0x80000
NVIC_DIS0_INT23
Interrupt 23 disable
0x800000
NVIC_DIS0_INT27
Interrupt 27 disable
0x8000000
NVIC_DIS0_INT31
Interrupt 31 disable
0x80000000
DIS1
Interrupt 32-54 Clear Enable
0x184
-1
read-write
n
0x0
0x0
NVIC_DIS1_INT
Interrupt Disable
0
23
NVIC_DIS1_INT32
Interrupt 32 disable
0x1
NVIC_DIS1_INT36
Interrupt 36 disable
0x10
NVIC_DIS1_INT40
Interrupt 40 disable
0x100
NVIC_DIS1_INT44
Interrupt 44 disable
0x1000
NVIC_DIS1_INT48
Interrupt 48 disable
0x10000
NVIC_DIS1_INT52
Interrupt 52 disable
0x100000
NVIC_DIS1_INT33
Interrupt 33 disable
0x2
NVIC_DIS1_INT37
Interrupt 37 disable
0x20
NVIC_DIS1_INT41
Interrupt 41 disable
0x200
NVIC_DIS1_INT45
Interrupt 45 disable
0x2000
NVIC_DIS1_INT49
Interrupt 49 disable
0x20000
NVIC_DIS1_INT53
Interrupt 53 disable
0x200000
NVIC_DIS1_INT34
Interrupt 34 disable
0x4
NVIC_DIS1_INT38
Interrupt 38 disable
0x40
NVIC_DIS1_INT42
Interrupt 42 disable
0x400
NVIC_DIS1_INT46
Interrupt 46 disable
0x4000
NVIC_DIS1_INT50
Interrupt 50 disable
0x40000
NVIC_DIS1_INT54
Interrupt 54 disable
0x400000
NVIC_DIS1_INT35
Interrupt 35 disable
0x8
NVIC_DIS1_INT39
Interrupt 39 disable
0x80
NVIC_DIS1_INT43
Interrupt 43 disable
0x800
NVIC_DIS1_INT47
Interrupt 47 disable
0x8000
NVIC_DIS1_INT51
Interrupt 51 disable
0x80000
EN0
Interrupt 0-31 Set Enable
0x100
-1
read-write
n
0x0
0x0
NVIC_EN0_INT
Interrupt Enable
0
32
NVIC_EN0_INT0
Interrupt 0 enable
0x1
NVIC_EN0_INT4
Interrupt 4 enable
0x10
NVIC_EN0_INT8
Interrupt 8 enable
0x100
NVIC_EN0_INT12
Interrupt 12 enable
0x1000
NVIC_EN0_INT16
Interrupt 16 enable
0x10000
NVIC_EN0_INT20
Interrupt 20 enable
0x100000
NVIC_EN0_INT24
Interrupt 24 enable
0x1000000
NVIC_EN0_INT28
Interrupt 28 enable
0x10000000
NVIC_EN0_INT1
Interrupt 1 enable
0x2
NVIC_EN0_INT5
Interrupt 5 enable
0x20
NVIC_EN0_INT9
Interrupt 9 enable
0x200
NVIC_EN0_INT13
Interrupt 13 enable
0x2000
NVIC_EN0_INT17
Interrupt 17 enable
0x20000
NVIC_EN0_INT21
Interrupt 21 enable
0x200000
NVIC_EN0_INT25
Interrupt 25 enable
0x2000000
NVIC_EN0_INT29
Interrupt 29 enable
0x20000000
NVIC_EN0_INT2
Interrupt 2 enable
0x4
NVIC_EN0_INT6
Interrupt 6 enable
0x40
NVIC_EN0_INT10
Interrupt 10 enable
0x400
NVIC_EN0_INT14
Interrupt 14 enable
0x4000
NVIC_EN0_INT18
Interrupt 18 enable
0x40000
NVIC_EN0_INT22
Interrupt 22 enable
0x400000
NVIC_EN0_INT26
Interrupt 26 enable
0x4000000
NVIC_EN0_INT30
Interrupt 30 enable
0x40000000
NVIC_EN0_INT3
Interrupt 3 enable
0x8
NVIC_EN0_INT7
Interrupt 7 enable
0x80
NVIC_EN0_INT11
Interrupt 11 enable
0x800
NVIC_EN0_INT15
Interrupt 15 enable
0x8000
NVIC_EN0_INT19
Interrupt 19 enable
0x80000
NVIC_EN0_INT23
Interrupt 23 enable
0x800000
NVIC_EN0_INT27
Interrupt 27 enable
0x8000000
NVIC_EN0_INT31
Interrupt 31 enable
0x80000000
EN1
Interrupt 32-54 Set Enable
0x104
-1
read-write
n
0x0
0x0
NVIC_EN1_INT
Interrupt Enable
0
23
NVIC_EN1_INT32
Interrupt 32 enable
0x1
NVIC_EN1_INT36
Interrupt 36 enable
0x10
NVIC_EN1_INT40
Interrupt 40 enable
0x100
NVIC_EN1_INT44
Interrupt 44 enable
0x1000
NVIC_EN1_INT48
Interrupt 48 enable
0x10000
NVIC_EN1_INT52
Interrupt 52 enable
0x100000
NVIC_EN1_INT33
Interrupt 33 enable
0x2
NVIC_EN1_INT37
Interrupt 37 enable
0x20
NVIC_EN1_INT41
Interrupt 41 enable
0x200
NVIC_EN1_INT45
Interrupt 45 enable
0x2000
NVIC_EN1_INT49
Interrupt 49 enable
0x20000
NVIC_EN1_INT53
Interrupt 53 enable
0x200000
NVIC_EN1_INT34
Interrupt 34 enable
0x4
NVIC_EN1_INT38
Interrupt 38 enable
0x40
NVIC_EN1_INT42
Interrupt 42 enable
0x400
NVIC_EN1_INT46
Interrupt 46 enable
0x4000
NVIC_EN1_INT50
Interrupt 50 enable
0x40000
NVIC_EN1_INT54
Interrupt 54 enable
0x400000
NVIC_EN1_INT35
Interrupt 35 enable
0x8
NVIC_EN1_INT39
Interrupt 39 enable
0x80
NVIC_EN1_INT43
Interrupt 43 enable
0x800
NVIC_EN1_INT47
Interrupt 47 enable
0x8000
NVIC_EN1_INT51
Interrupt 51 enable
0x80000
FAULT_ADDR
Bus Fault Address
0xD38
-1
read-write
n
0x0
0x0
NVIC_FAULT_ADDR
Fault Address
0
32
FAULT_STAT
Configurable Fault Status
0xD28
-1
read-write
n
0x0
0x0
NVIC_FAULT_STAT_BFARV
Bus Fault Address Register Valid
15
16
NVIC_FAULT_STAT_BSTKE
Stack Bus Fault
12
13
NVIC_FAULT_STAT_BUSTKE
Unstack Bus Fault
11
12
NVIC_FAULT_STAT_DERR
Data Access Violation
1
2
NVIC_FAULT_STAT_DIV0
Divide-by-Zero Usage Fault
25
26
NVIC_FAULT_STAT_IBUS
Instruction Bus Error
8
9
NVIC_FAULT_STAT_IERR
Instruction Access Violation
0
1
NVIC_FAULT_STAT_IMPRE
Imprecise Data Bus Error
10
11
NVIC_FAULT_STAT_INVPC
Invalid PC Load Usage Fault
18
19
NVIC_FAULT_STAT_INVSTAT
Invalid State Usage Fault
17
18
NVIC_FAULT_STAT_MMARV
Memory Management Fault Address Register Valid
7
8
NVIC_FAULT_STAT_MSTKE
Stack Access Violation
4
5
NVIC_FAULT_STAT_MUSTKE
Unstack Access Violation
3
4
NVIC_FAULT_STAT_NOCP
No Coprocessor Usage Fault
19
20
NVIC_FAULT_STAT_PRECISE
Precise Data Bus Error
9
10
NVIC_FAULT_STAT_UNALIGN
Unaligned Access Usage Fault
24
25
NVIC_FAULT_STAT_UNDEF
Undefined Instruction Usage Fault
16
17
HFAULT_STAT
Hard Fault Status
0xD2C
-1
read-write
n
0x0
0x0
NVIC_HFAULT_STAT_DBG
Debug Event
31
32
NVIC_HFAULT_STAT_FORCED
Forced Hard Fault
30
31
NVIC_HFAULT_STAT_VECT
Vector Table Read Fault
1
2
INT_CTRL
Interrupt Control and State
0xD04
-1
read-write
n
0x0
0x0
NVIC_INT_CTRL_ISR_PEND
Interrupt Pending
22
23
NVIC_INT_CTRL_ISR_PRE
Debug Interrupt Handling
23
24
NVIC_INT_CTRL_NMI_SET
NMI Set Pending
31
32
NVIC_INT_CTRL_PENDSTCLR
SysTick Clear Pending
25
26
NVIC_INT_CTRL_PENDSTSET
SysTick Set Pending
26
27
NVIC_INT_CTRL_PEND_SV
PendSV Set Pending
28
29
NVIC_INT_CTRL_RET_BASE
Return to Base
11
12
NVIC_INT_CTRL_UNPEND_SV
PendSV Clear Pending
27
28
NVIC_INT_CTRL_VEC_ACT
Interrupt Pending Vector Number
0
7
NVIC_INT_CTRL_VEC_PEN
Interrupt Pending Vector Number
12
19
NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x2
NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x3
NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x4
NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x5
NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0x6
NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xb
NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xe
NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
0xf
INT_TYPE
Interrupt Controller Type Reg
0x4
-1
read-write
n
0x0
0x0
NVIC_INT_TYPE_LINES
Number of interrupt lines (x32)
0
5
MM_ADDR
Memory Management Fault Address
0xD34
-1
read-write
n
0x0
0x0
NVIC_MM_ADDR
Fault Address
0
32
MPU_ATTR
MPU Region Attribute and Size
0xDA0
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR_AP
Access Privilege
24
27
NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x0
NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x1
NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x2
NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x3
NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x5
NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
0x6
NVIC_MPU_ATTR_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x10
NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x11
NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x12
NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x13
NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x14
NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x15
NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x16
NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x17
NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x18
NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x19
NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1a
NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1b
NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1c
NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1d
NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1e
NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
0x1f
NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x4
NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x5
NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x6
NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x7
NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x8
NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0x9
NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xa
NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xb
NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xc
NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xd
NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xe
NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0xf
NVIC_MPU_ATTR_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x1
NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x10
NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x2
NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x20
NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x4
NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x40
NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x8
NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
0x80
NVIC_MPU_ATTR_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR_XN
Instruction Access Disable
28
29
MPU_ATTR1
MPU Region Attribute and Size Alias 1
0xDA8
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR1_AP
Access Privilege
24
27
NVIC_MPU_ATTR1_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR1_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR1_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR1_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR1_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR1_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR1_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR1_XN
Instruction Access Disable
28
29
MPU_ATTR2
MPU Region Attribute and Size Alias 2
0xDB0
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR2_AP
Access Privilege
24
27
NVIC_MPU_ATTR2_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR2_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR2_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR2_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR2_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR2_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR2_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR2_XN
Instruction Access Disable
28
29
MPU_ATTR3
MPU Region Attribute and Size Alias 3
0xDB8
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR3_AP
Access Privilege
24
27
NVIC_MPU_ATTR3_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR3_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR3_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR3_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR3_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR3_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR3_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR3_XN
Instruction Access Disable
28
29
MPU_BASE
MPU Region Base Address
0xD9C
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE_REGION
Region Number
0
3
NVIC_MPU_BASE_VALID
Region Number Valid
4
5
MPU_BASE1
MPU Region Base Address Alias 1
0xDA4
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE1_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE1_REGION
Region Number
0
3
NVIC_MPU_BASE1_VALID
Region Number Valid
4
5
MPU_BASE2
MPU Region Base Address Alias 2
0xDAC
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE2_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE2_REGION
Region Number
0
3
NVIC_MPU_BASE2_VALID
Region Number Valid
4
5
MPU_BASE3
MPU Region Base Address Alias 3
0xDB4
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE3_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE3_REGION
Region Number
0
3
NVIC_MPU_BASE3_VALID
Region Number Valid
4
5
MPU_CTRL
MPU Control
0xD94
-1
read-write
n
0x0
0x0
NVIC_MPU_CTRL_ENABLE
MPU Enable
0
1
NVIC_MPU_CTRL_HFNMIENA
MPU Enabled During Faults
1
2
NVIC_MPU_CTRL_PRIVDEFEN
MPU Default Region
2
3
MPU_NUMBER
MPU Region Number
0xD98
-1
read-write
n
0x0
0x0
NVIC_MPU_NUMBER
MPU Region to Access
0
3
MPU_TYPE
MPU Type
0xD90
-1
read-write
n
0x0
0x0
NVIC_MPU_TYPE_DREGION
Number of D Regions
8
16
NVIC_MPU_TYPE_IREGION
Number of I Regions
16
24
NVIC_MPU_TYPE_SEPARATE
Separate or Unified MPU
0
1
NVICACTIVE0
Interrupt 0-31 Active Bit
0x300
read-write
n
0x0
0x0
NVIC_ACTIVE0_INT
Interrupt Active
0
32
NVIC_ACTIVE0_INT0
Interrupt 0 active
0x1
NVIC_ACTIVE0_INT4
Interrupt 4 active
0x10
NVIC_ACTIVE0_INT8
Interrupt 8 active
0x100
NVIC_ACTIVE0_INT12
Interrupt 12 active
0x1000
NVIC_ACTIVE0_INT16
Interrupt 16 active
0x10000
NVIC_ACTIVE0_INT20
Interrupt 20 active
0x100000
NVIC_ACTIVE0_INT24
Interrupt 24 active
0x1000000
NVIC_ACTIVE0_INT28
Interrupt 28 active
0x10000000
NVIC_ACTIVE0_INT1
Interrupt 1 active
0x2
NVIC_ACTIVE0_INT5
Interrupt 5 active
0x20
NVIC_ACTIVE0_INT9
Interrupt 9 active
0x200
NVIC_ACTIVE0_INT13
Interrupt 13 active
0x2000
NVIC_ACTIVE0_INT17
Interrupt 17 active
0x20000
NVIC_ACTIVE0_INT21
Interrupt 21 active
0x200000
NVIC_ACTIVE0_INT25
Interrupt 25 active
0x2000000
NVIC_ACTIVE0_INT29
Interrupt 29 active
0x20000000
NVIC_ACTIVE0_INT2
Interrupt 2 active
0x4
NVIC_ACTIVE0_INT6
Interrupt 6 active
0x40
NVIC_ACTIVE0_INT10
Interrupt 10 active
0x400
NVIC_ACTIVE0_INT14
Interrupt 14 active
0x4000
NVIC_ACTIVE0_INT18
Interrupt 18 active
0x40000
NVIC_ACTIVE0_INT22
Interrupt 22 active
0x400000
NVIC_ACTIVE0_INT26
Interrupt 26 active
0x4000000
NVIC_ACTIVE0_INT30
Interrupt 30 active
0x40000000
NVIC_ACTIVE0_INT3
Interrupt 3 active
0x8
NVIC_ACTIVE0_INT7
Interrupt 7 active
0x80
NVIC_ACTIVE0_INT11
Interrupt 11 active
0x800
NVIC_ACTIVE0_INT15
Interrupt 15 active
0x8000
NVIC_ACTIVE0_INT19
Interrupt 19 active
0x80000
NVIC_ACTIVE0_INT23
Interrupt 23 active
0x800000
NVIC_ACTIVE0_INT27
Interrupt 27 active
0x8000000
NVIC_ACTIVE0_INT31
Interrupt 31 active
0x80000000
NVICACTIVE1
Interrupt 32-54 Active Bit
0x304
read-write
n
0x0
0x0
NVIC_ACTIVE1_INT
Interrupt Active
0
23
NVIC_ACTIVE1_INT32
Interrupt 32 active
0x1
NVIC_ACTIVE1_INT36
Interrupt 36 active
0x10
NVIC_ACTIVE1_INT40
Interrupt 40 active
0x100
NVIC_ACTIVE1_INT44
Interrupt 44 active
0x1000
NVIC_ACTIVE1_INT48
Interrupt 48 active
0x10000
NVIC_ACTIVE1_INT52
Interrupt 52 active
0x100000
NVIC_ACTIVE1_INT33
Interrupt 33 active
0x2
NVIC_ACTIVE1_INT37
Interrupt 37 active
0x20
NVIC_ACTIVE1_INT41
Interrupt 41 active
0x200
NVIC_ACTIVE1_INT45
Interrupt 45 active
0x2000
NVIC_ACTIVE1_INT49
Interrupt 49 active
0x20000
NVIC_ACTIVE1_INT53
Interrupt 53 active
0x200000
NVIC_ACTIVE1_INT34
Interrupt 34 active
0x4
NVIC_ACTIVE1_INT38
Interrupt 38 active
0x40
NVIC_ACTIVE1_INT42
Interrupt 42 active
0x400
NVIC_ACTIVE1_INT46
Interrupt 46 active
0x4000
NVIC_ACTIVE1_INT50
Interrupt 50 active
0x40000
NVIC_ACTIVE1_INT54
Interrupt 54 active
0x400000
NVIC_ACTIVE1_INT35
Interrupt 35 active
0x8
NVIC_ACTIVE1_INT39
Interrupt 39 active
0x80
NVIC_ACTIVE1_INT43
Interrupt 43 active
0x800
NVIC_ACTIVE1_INT47
Interrupt 47 active
0x8000
NVIC_ACTIVE1_INT51
Interrupt 51 active
0x80000
NVICACTLR
Auxiliary Control
0x8
read-write
n
0x0
0x0
NVIC_ACTLR_DISFOLD
Disable IT Folding
2
3
NVIC_ACTLR_DISMCYC
Disable Interrupts of Multiple Cycle Instructions
0
1
NVIC_ACTLR_DISWBUF
Disable Write Buffer
1
2
NVICAPINT
Application Interrupt and Reset Control
0xD0C
read-write
n
0x0
0x0
NVIC_APINT_ENDIANESS
Data Endianess
15
16
NVIC_APINT_PRIGROUP
Interrupt Priority Grouping
8
11
NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x0
NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x1
NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x2
NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x3
NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x4
NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x5
NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x6
NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
0x7
NVIC_APINT_SYSRESETREQ
System Reset Request
2
3
NVIC_APINT_VECTKEY
Register Key
16
32
NVIC_APINT_VECTKEY
Vector key
0x5fa
NVIC_APINT_VECT_CLR_ACT
Clear Active NMI / Fault
1
2
NVIC_APINT_VECT_RESET
System Reset
0
1
NVICCFG_CTRL
Configuration and Control
0xD14
read-write
n
0x0
0x0
NVIC_CFG_CTRL_BASE_THR
Thread State Control
0
1
NVIC_CFG_CTRL_BFHFNMIGN
Ignore Bus Fault in NMI and Fault
8
9
NVIC_CFG_CTRL_DIV0
Trap on Divide by 0
4
5
NVIC_CFG_CTRL_MAIN_PEND
Allow Main Interrupt Trigger
1
2
NVIC_CFG_CTRL_STKALIGN
Stack Alignment on Exception Entry
9
10
NVIC_CFG_CTRL_UNALIGNED
Trap on Unaligned Access
3
4
NVICCPUID
CPU ID Base
0xD00
read-write
n
0x0
0x0
NVIC_CPUID_CON
Constant
16
20
NVIC_CPUID_IMP
Implementer Code
24
32
NVIC_CPUID_IMP_ARM
ARM
0x41
NVIC_CPUID_PARTNO
Part Number
4
16
NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
0xc23
NVIC_CPUID_REV
Revision Number
0
4
NVIC_CPUID_VAR
Variant Number
20
24
NVICDBG_CTRL
Debug Control and Status Reg
0xDF0
read-write
n
0x0
0x0
NVIC_DBG_CTRL_C_DEBUGEN
Enable debug
0
1
NVIC_DBG_CTRL_C_HALT
Halt the core
1
2
NVIC_DBG_CTRL_C_MASKINT
Mask interrupts when stepping
3
4
NVIC_DBG_CTRL_C_SNAPSTALL
Breaks a stalled load/store
5
6
NVIC_DBG_CTRL_C_STEP
Step the core
2
3
NVIC_DBG_CTRL_S_HALT
Core status on halt
17
18
NVIC_DBG_CTRL_S_LOCKUP
Core is locked up
19
20
NVIC_DBG_CTRL_S_REGRDY
Register read/write available
16
17
NVIC_DBG_CTRL_S_RESET_ST
Core has reset since last read
25
26
NVIC_DBG_CTRL_S_RETIRE_ST
Core has executed insruction since last read
24
25
NVIC_DBG_CTRL_S_SLEEP
Core is sleeping
18
19
NVICDBG_DATA
Debug Core Register Data
0xDF8
read-write
n
0x0
0x0
NVIC_DBG_DATA
Data temporary cache
0
32
NVICDBG_INT
Debug Reset Interrupt Control
0xDFC
read-write
n
0x0
0x0
NVIC_DBG_INT_BUSERR
Debug trap on bus error
8
9
NVIC_DBG_INT_CHKERR
Debug trap on usage fault check
6
7
NVIC_DBG_INT_HARDERR
Debug trap on hard fault
10
11
NVIC_DBG_INT_INTERR
Debug trap on interrupt errors
9
10
NVIC_DBG_INT_MMERR
Debug trap on mem manage fault
4
5
NVIC_DBG_INT_NOCPERR
Debug trap on coprocessor error
5
6
NVIC_DBG_INT_RESET
Core reset status
3
4
NVIC_DBG_INT_RSTPENDCLR
Clear pending core reset
2
3
NVIC_DBG_INT_RSTPENDING
Core reset is pending
1
2
NVIC_DBG_INT_RSTVCATCH
Reset vector catch
0
1
NVIC_DBG_INT_STATERR
Debug trap on usage fault state
7
8
NVICDBG_XFER
Debug Core Reg. Transfer Select
0xDF4
read-write
n
0x0
0x0
NVIC_DBG_XFER_REG_SEL
Register
0
5
NVIC_DBG_XFER_REG_R0
Register R0
0x0
NVIC_DBG_XFER_REG_R1
Register R1
0x1
NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x10
NVIC_DBG_XFER_REG_MSP
Main SP
0x11
NVIC_DBG_XFER_REG_PSP
Process SP
0x12
NVIC_DBG_XFER_REG_DSP
Deep SP
0x13
NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
0x14
NVIC_DBG_XFER_REG_R2
Register R2
0x2
NVIC_DBG_XFER_REG_R3
Register R3
0x3
NVIC_DBG_XFER_REG_R4
Register R4
0x4
NVIC_DBG_XFER_REG_R5
Register R5
0x5
NVIC_DBG_XFER_REG_R6
Register R6
0x6
NVIC_DBG_XFER_REG_R7
Register R7
0x7
NVIC_DBG_XFER_REG_R8
Register R8
0x8
NVIC_DBG_XFER_REG_R9
Register R9
0x9
NVIC_DBG_XFER_REG_R10
Register R10
0xa
NVIC_DBG_XFER_REG_R11
Register R11
0xb
NVIC_DBG_XFER_REG_R12
Register R12
0xc
NVIC_DBG_XFER_REG_R13
Register R13
0xd
NVIC_DBG_XFER_REG_R14
Register R14
0xe
NVIC_DBG_XFER_REG_R15
Register R15
0xf
NVIC_DBG_XFER_REG_WNR
Write or not read
16
17
NVICDEBUG_STAT
Debug Status Register
0xD30
read-write
n
0x0
0x0
NVIC_DEBUG_STAT_BKPT
Breakpoint instruction
1
2
NVIC_DEBUG_STAT_DWTTRAP
DWT match
2
3
NVIC_DEBUG_STAT_EXTRNL
EDBGRQ asserted
4
5
NVIC_DEBUG_STAT_HALTED
Halt request
0
1
NVIC_DEBUG_STAT_VCATCH
Vector catch
3
4
NVICDIS0
Interrupt 0-31 Clear Enable
0x180
read-write
n
0x0
0x0
NVIC_DIS0_INT
Interrupt Disable
0
32
NVIC_DIS0_INT0
Interrupt 0 disable
0x1
NVIC_DIS0_INT4
Interrupt 4 disable
0x10
NVIC_DIS0_INT8
Interrupt 8 disable
0x100
NVIC_DIS0_INT12
Interrupt 12 disable
0x1000
NVIC_DIS0_INT16
Interrupt 16 disable
0x10000
NVIC_DIS0_INT20
Interrupt 20 disable
0x100000
NVIC_DIS0_INT24
Interrupt 24 disable
0x1000000
NVIC_DIS0_INT28
Interrupt 28 disable
0x10000000
NVIC_DIS0_INT1
Interrupt 1 disable
0x2
NVIC_DIS0_INT5
Interrupt 5 disable
0x20
NVIC_DIS0_INT9
Interrupt 9 disable
0x200
NVIC_DIS0_INT13
Interrupt 13 disable
0x2000
NVIC_DIS0_INT17
Interrupt 17 disable
0x20000
NVIC_DIS0_INT21
Interrupt 21 disable
0x200000
NVIC_DIS0_INT25
Interrupt 25 disable
0x2000000
NVIC_DIS0_INT29
Interrupt 29 disable
0x20000000
NVIC_DIS0_INT2
Interrupt 2 disable
0x4
NVIC_DIS0_INT6
Interrupt 6 disable
0x40
NVIC_DIS0_INT10
Interrupt 10 disable
0x400
NVIC_DIS0_INT14
Interrupt 14 disable
0x4000
NVIC_DIS0_INT18
Interrupt 18 disable
0x40000
NVIC_DIS0_INT22
Interrupt 22 disable
0x400000
NVIC_DIS0_INT26
Interrupt 26 disable
0x4000000
NVIC_DIS0_INT30
Interrupt 30 disable
0x40000000
NVIC_DIS0_INT3
Interrupt 3 disable
0x8
NVIC_DIS0_INT7
Interrupt 7 disable
0x80
NVIC_DIS0_INT11
Interrupt 11 disable
0x800
NVIC_DIS0_INT15
Interrupt 15 disable
0x8000
NVIC_DIS0_INT19
Interrupt 19 disable
0x80000
NVIC_DIS0_INT23
Interrupt 23 disable
0x800000
NVIC_DIS0_INT27
Interrupt 27 disable
0x8000000
NVIC_DIS0_INT31
Interrupt 31 disable
0x80000000
NVICDIS1
Interrupt 32-54 Clear Enable
0x184
read-write
n
0x0
0x0
NVIC_DIS1_INT
Interrupt Disable
0
23
NVIC_DIS1_INT32
Interrupt 32 disable
0x1
NVIC_DIS1_INT36
Interrupt 36 disable
0x10
NVIC_DIS1_INT40
Interrupt 40 disable
0x100
NVIC_DIS1_INT44
Interrupt 44 disable
0x1000
NVIC_DIS1_INT48
Interrupt 48 disable
0x10000
NVIC_DIS1_INT52
Interrupt 52 disable
0x100000
NVIC_DIS1_INT33
Interrupt 33 disable
0x2
NVIC_DIS1_INT37
Interrupt 37 disable
0x20
NVIC_DIS1_INT41
Interrupt 41 disable
0x200
NVIC_DIS1_INT45
Interrupt 45 disable
0x2000
NVIC_DIS1_INT49
Interrupt 49 disable
0x20000
NVIC_DIS1_INT53
Interrupt 53 disable
0x200000
NVIC_DIS1_INT34
Interrupt 34 disable
0x4
NVIC_DIS1_INT38
Interrupt 38 disable
0x40
NVIC_DIS1_INT42
Interrupt 42 disable
0x400
NVIC_DIS1_INT46
Interrupt 46 disable
0x4000
NVIC_DIS1_INT50
Interrupt 50 disable
0x40000
NVIC_DIS1_INT54
Interrupt 54 disable
0x400000
NVIC_DIS1_INT35
Interrupt 35 disable
0x8
NVIC_DIS1_INT39
Interrupt 39 disable
0x80
NVIC_DIS1_INT43
Interrupt 43 disable
0x800
NVIC_DIS1_INT47
Interrupt 47 disable
0x8000
NVIC_DIS1_INT51
Interrupt 51 disable
0x80000
NVICEN0
Interrupt 0-31 Set Enable
0x100
read-write
n
0x0
0x0
NVIC_EN0_INT
Interrupt Enable
0
32
NVIC_EN0_INT0
Interrupt 0 enable
0x1
NVIC_EN0_INT4
Interrupt 4 enable
0x10
NVIC_EN0_INT8
Interrupt 8 enable
0x100
NVIC_EN0_INT12
Interrupt 12 enable
0x1000
NVIC_EN0_INT16
Interrupt 16 enable
0x10000
NVIC_EN0_INT20
Interrupt 20 enable
0x100000
NVIC_EN0_INT24
Interrupt 24 enable
0x1000000
NVIC_EN0_INT28
Interrupt 28 enable
0x10000000
NVIC_EN0_INT1
Interrupt 1 enable
0x2
NVIC_EN0_INT5
Interrupt 5 enable
0x20
NVIC_EN0_INT9
Interrupt 9 enable
0x200
NVIC_EN0_INT13
Interrupt 13 enable
0x2000
NVIC_EN0_INT17
Interrupt 17 enable
0x20000
NVIC_EN0_INT21
Interrupt 21 enable
0x200000
NVIC_EN0_INT25
Interrupt 25 enable
0x2000000
NVIC_EN0_INT29
Interrupt 29 enable
0x20000000
NVIC_EN0_INT2
Interrupt 2 enable
0x4
NVIC_EN0_INT6
Interrupt 6 enable
0x40
NVIC_EN0_INT10
Interrupt 10 enable
0x400
NVIC_EN0_INT14
Interrupt 14 enable
0x4000
NVIC_EN0_INT18
Interrupt 18 enable
0x40000
NVIC_EN0_INT22
Interrupt 22 enable
0x400000
NVIC_EN0_INT26
Interrupt 26 enable
0x4000000
NVIC_EN0_INT30
Interrupt 30 enable
0x40000000
NVIC_EN0_INT3
Interrupt 3 enable
0x8
NVIC_EN0_INT7
Interrupt 7 enable
0x80
NVIC_EN0_INT11
Interrupt 11 enable
0x800
NVIC_EN0_INT15
Interrupt 15 enable
0x8000
NVIC_EN0_INT19
Interrupt 19 enable
0x80000
NVIC_EN0_INT23
Interrupt 23 enable
0x800000
NVIC_EN0_INT27
Interrupt 27 enable
0x8000000
NVIC_EN0_INT31
Interrupt 31 enable
0x80000000
NVICEN1
Interrupt 32-54 Set Enable
0x104
read-write
n
0x0
0x0
NVIC_EN1_INT
Interrupt Enable
0
23
NVIC_EN1_INT32
Interrupt 32 enable
0x1
NVIC_EN1_INT36
Interrupt 36 enable
0x10
NVIC_EN1_INT40
Interrupt 40 enable
0x100
NVIC_EN1_INT44
Interrupt 44 enable
0x1000
NVIC_EN1_INT48
Interrupt 48 enable
0x10000
NVIC_EN1_INT52
Interrupt 52 enable
0x100000
NVIC_EN1_INT33
Interrupt 33 enable
0x2
NVIC_EN1_INT37
Interrupt 37 enable
0x20
NVIC_EN1_INT41
Interrupt 41 enable
0x200
NVIC_EN1_INT45
Interrupt 45 enable
0x2000
NVIC_EN1_INT49
Interrupt 49 enable
0x20000
NVIC_EN1_INT53
Interrupt 53 enable
0x200000
NVIC_EN1_INT34
Interrupt 34 enable
0x4
NVIC_EN1_INT38
Interrupt 38 enable
0x40
NVIC_EN1_INT42
Interrupt 42 enable
0x400
NVIC_EN1_INT46
Interrupt 46 enable
0x4000
NVIC_EN1_INT50
Interrupt 50 enable
0x40000
NVIC_EN1_INT54
Interrupt 54 enable
0x400000
NVIC_EN1_INT35
Interrupt 35 enable
0x8
NVIC_EN1_INT39
Interrupt 39 enable
0x80
NVIC_EN1_INT43
Interrupt 43 enable
0x800
NVIC_EN1_INT47
Interrupt 47 enable
0x8000
NVIC_EN1_INT51
Interrupt 51 enable
0x80000
NVICFAULT_ADDR
Bus Fault Address
0xD38
read-write
n
0x0
0x0
NVIC_FAULT_ADDR
Fault Address
0
32
NVICFAULT_STAT
Configurable Fault Status
0xD28
read-write
n
0x0
0x0
NVIC_FAULT_STAT_BFARV
Bus Fault Address Register Valid
15
16
NVIC_FAULT_STAT_BSTKE
Stack Bus Fault
12
13
NVIC_FAULT_STAT_BUSTKE
Unstack Bus Fault
11
12
NVIC_FAULT_STAT_DERR
Data Access Violation
1
2
NVIC_FAULT_STAT_DIV0
Divide-by-Zero Usage Fault
25
26
NVIC_FAULT_STAT_IBUS
Instruction Bus Error
8
9
NVIC_FAULT_STAT_IERR
Instruction Access Violation
0
1
NVIC_FAULT_STAT_IMPRE
Imprecise Data Bus Error
10
11
NVIC_FAULT_STAT_INVPC
Invalid PC Load Usage Fault
18
19
NVIC_FAULT_STAT_INVSTAT
Invalid State Usage Fault
17
18
NVIC_FAULT_STAT_MMARV
Memory Management Fault Address Register Valid
7
8
NVIC_FAULT_STAT_MSTKE
Stack Access Violation
4
5
NVIC_FAULT_STAT_MUSTKE
Unstack Access Violation
3
4
NVIC_FAULT_STAT_NOCP
No Coprocessor Usage Fault
19
20
NVIC_FAULT_STAT_PRECISE
Precise Data Bus Error
9
10
NVIC_FAULT_STAT_UNALIGN
Unaligned Access Usage Fault
24
25
NVIC_FAULT_STAT_UNDEF
Undefined Instruction Usage Fault
16
17
NVICHFAULT_STAT
Hard Fault Status
0xD2C
read-write
n
0x0
0x0
NVIC_HFAULT_STAT_DBG
Debug Event
31
32
NVIC_HFAULT_STAT_FORCED
Forced Hard Fault
30
31
NVIC_HFAULT_STAT_VECT
Vector Table Read Fault
1
2
NVICINT_CTRL
Interrupt Control and State
0xD04
read-write
n
0x0
0x0
NVIC_INT_CTRL_ISR_PEND
Interrupt Pending
22
23
NVIC_INT_CTRL_ISR_PRE
Debug Interrupt Handling
23
24
NVIC_INT_CTRL_NMI_SET
NMI Set Pending
31
32
NVIC_INT_CTRL_PENDSTCLR
SysTick Clear Pending
25
26
NVIC_INT_CTRL_PENDSTSET
SysTick Set Pending
26
27
NVIC_INT_CTRL_PEND_SV
PendSV Set Pending
28
29
NVIC_INT_CTRL_RET_BASE
Return to Base
11
12
NVIC_INT_CTRL_UNPEND_SV
PendSV Clear Pending
27
28
NVIC_INT_CTRL_VEC_ACT
Interrupt Pending Vector Number
0
7
NVIC_INT_CTRL_VEC_PEN
Interrupt Pending Vector Number
12
19
NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x2
NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x3
NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x4
NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x5
NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0x6
NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xb
NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xe
NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
0xf
NVICINT_TYPE
Interrupt Controller Type Reg
0x4
read-write
n
0x0
0x0
NVIC_INT_TYPE_LINES
Number of interrupt lines (x32)
0
5
NVICMM_ADDR
Memory Management Fault Address
0xD34
read-write
n
0x0
0x0
NVIC_MM_ADDR
Fault Address
0
32
NVICMPU_ATTR
MPU Region Attribute and Size
0xDA0
read-write
n
0x0
0x0
NVIC_MPU_ATTR_AP
Access Privilege
24
27
NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x0
NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x1
NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x2
NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x3
NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x5
NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
0x6
NVIC_MPU_ATTR_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x10
NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x11
NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x12
NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x13
NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x14
NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x15
NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x16
NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x17
NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x18
NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x19
NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1a
NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1b
NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1c
NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1d
NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1e
NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
0x1f
NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x4
NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x5
NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x6
NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x7
NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x8
NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0x9
NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xa
NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xb
NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xc
NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xd
NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xe
NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0xf
NVIC_MPU_ATTR_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x1
NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x10
NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x2
NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x20
NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x4
NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x40
NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x8
NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
0x80
NVIC_MPU_ATTR_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR_XN
Instruction Access Disable
28
29
NVICMPU_ATTR1
MPU Region Attribute and Size Alias 1
0xDA8
read-write
n
0x0
0x0
NVIC_MPU_ATTR1_AP
Access Privilege
24
27
NVIC_MPU_ATTR1_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR1_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR1_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR1_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR1_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR1_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR1_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR1_XN
Instruction Access Disable
28
29
NVICMPU_ATTR2
MPU Region Attribute and Size Alias 2
0xDB0
read-write
n
0x0
0x0
NVIC_MPU_ATTR2_AP
Access Privilege
24
27
NVIC_MPU_ATTR2_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR2_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR2_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR2_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR2_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR2_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR2_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR2_XN
Instruction Access Disable
28
29
NVICMPU_ATTR3
MPU Region Attribute and Size Alias 3
0xDB8
read-write
n
0x0
0x0
NVIC_MPU_ATTR3_AP
Access Privilege
24
27
NVIC_MPU_ATTR3_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR3_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR3_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR3_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR3_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR3_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR3_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR3_XN
Instruction Access Disable
28
29
NVICMPU_BASE
MPU Region Base Address
0xD9C
read-write
n
0x0
0x0
NVIC_MPU_BASE_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE_REGION
Region Number
0
3
NVIC_MPU_BASE_VALID
Region Number Valid
4
5
NVICMPU_BASE1
MPU Region Base Address Alias 1
0xDA4
read-write
n
0x0
0x0
NVIC_MPU_BASE1_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE1_REGION
Region Number
0
3
NVIC_MPU_BASE1_VALID
Region Number Valid
4
5
NVICMPU_BASE2
MPU Region Base Address Alias 2
0xDAC
read-write
n
0x0
0x0
NVIC_MPU_BASE2_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE2_REGION
Region Number
0
3
NVIC_MPU_BASE2_VALID
Region Number Valid
4
5
NVICMPU_BASE3
MPU Region Base Address Alias 3
0xDB4
read-write
n
0x0
0x0
NVIC_MPU_BASE3_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE3_REGION
Region Number
0
3
NVIC_MPU_BASE3_VALID
Region Number Valid
4
5
NVICMPU_CTRL
MPU Control
0xD94
read-write
n
0x0
0x0
NVIC_MPU_CTRL_ENABLE
MPU Enable
0
1
NVIC_MPU_CTRL_HFNMIENA
MPU Enabled During Faults
1
2
NVIC_MPU_CTRL_PRIVDEFEN
MPU Default Region
2
3
NVICMPU_NUMBER
MPU Region Number
0xD98
read-write
n
0x0
0x0
NVIC_MPU_NUMBER
MPU Region to Access
0
3
NVICMPU_TYPE
MPU Type
0xD90
read-write
n
0x0
0x0
NVIC_MPU_TYPE_DREGION
Number of D Regions
8
16
NVIC_MPU_TYPE_IREGION
Number of I Regions
16
24
NVIC_MPU_TYPE_SEPARATE
Separate or Unified MPU
0
1
NVICPEND0
Interrupt 0-31 Set Pending
0x200
read-write
n
0x0
0x0
NVIC_PEND0_INT
Interrupt Set Pending
0
32
NVIC_PEND0_INT0
Interrupt 0 pend
0x1
NVIC_PEND0_INT4
Interrupt 4 pend
0x10
NVIC_PEND0_INT8
Interrupt 8 pend
0x100
NVIC_PEND0_INT12
Interrupt 12 pend
0x1000
NVIC_PEND0_INT16
Interrupt 16 pend
0x10000
NVIC_PEND0_INT20
Interrupt 20 pend
0x100000
NVIC_PEND0_INT24
Interrupt 24 pend
0x1000000
NVIC_PEND0_INT28
Interrupt 28 pend
0x10000000
NVIC_PEND0_INT1
Interrupt 1 pend
0x2
NVIC_PEND0_INT5
Interrupt 5 pend
0x20
NVIC_PEND0_INT9
Interrupt 9 pend
0x200
NVIC_PEND0_INT13
Interrupt 13 pend
0x2000
NVIC_PEND0_INT17
Interrupt 17 pend
0x20000
NVIC_PEND0_INT21
Interrupt 21 pend
0x200000
NVIC_PEND0_INT25
Interrupt 25 pend
0x2000000
NVIC_PEND0_INT29
Interrupt 29 pend
0x20000000
NVIC_PEND0_INT2
Interrupt 2 pend
0x4
NVIC_PEND0_INT6
Interrupt 6 pend
0x40
NVIC_PEND0_INT10
Interrupt 10 pend
0x400
NVIC_PEND0_INT14
Interrupt 14 pend
0x4000
NVIC_PEND0_INT18
Interrupt 18 pend
0x40000
NVIC_PEND0_INT22
Interrupt 22 pend
0x400000
NVIC_PEND0_INT26
Interrupt 26 pend
0x4000000
NVIC_PEND0_INT30
Interrupt 30 pend
0x40000000
NVIC_PEND0_INT3
Interrupt 3 pend
0x8
NVIC_PEND0_INT7
Interrupt 7 pend
0x80
NVIC_PEND0_INT11
Interrupt 11 pend
0x800
NVIC_PEND0_INT15
Interrupt 15 pend
0x8000
NVIC_PEND0_INT19
Interrupt 19 pend
0x80000
NVIC_PEND0_INT23
Interrupt 23 pend
0x800000
NVIC_PEND0_INT27
Interrupt 27 pend
0x8000000
NVIC_PEND0_INT31
Interrupt 31 pend
0x80000000
NVICPEND1
Interrupt 32-54 Set Pending
0x204
read-write
n
0x0
0x0
NVIC_PEND1_INT
Interrupt Set Pending
0
23
NVIC_PEND1_INT32
Interrupt 32 pend
0x1
NVIC_PEND1_INT36
Interrupt 36 pend
0x10
NVIC_PEND1_INT40
Interrupt 40 pend
0x100
NVIC_PEND1_INT44
Interrupt 44 pend
0x1000
NVIC_PEND1_INT48
Interrupt 48 pend
0x10000
NVIC_PEND1_INT52
Interrupt 52 pend
0x100000
NVIC_PEND1_INT33
Interrupt 33 pend
0x2
NVIC_PEND1_INT37
Interrupt 37 pend
0x20
NVIC_PEND1_INT41
Interrupt 41 pend
0x200
NVIC_PEND1_INT45
Interrupt 45 pend
0x2000
NVIC_PEND1_INT49
Interrupt 49 pend
0x20000
NVIC_PEND1_INT53
Interrupt 53 pend
0x200000
NVIC_PEND1_INT34
Interrupt 34 pend
0x4
NVIC_PEND1_INT38
Interrupt 38 pend
0x40
NVIC_PEND1_INT42
Interrupt 42 pend
0x400
NVIC_PEND1_INT46
Interrupt 46 pend
0x4000
NVIC_PEND1_INT50
Interrupt 50 pend
0x40000
NVIC_PEND1_INT54
Interrupt 54 pend
0x400000
NVIC_PEND1_INT35
Interrupt 35 pend
0x8
NVIC_PEND1_INT39
Interrupt 39 pend
0x80
NVIC_PEND1_INT43
Interrupt 43 pend
0x800
NVIC_PEND1_INT47
Interrupt 47 pend
0x8000
NVIC_PEND1_INT51
Interrupt 51 pend
0x80000
NVICPRI0
Interrupt 0-3 Priority
0x400
read-write
n
0x0
0x0
NVIC_PRI0_INT0
Interrupt 0 Priority Mask
5
8
NVIC_PRI0_INT1
Interrupt 1 Priority Mask
13
16
NVIC_PRI0_INT2
Interrupt 2 Priority Mask
21
24
NVIC_PRI0_INT3
Interrupt 3 Priority Mask
29
32
NVICPRI1
Interrupt 4-7 Priority
0x404
read-write
n
0x0
0x0
NVIC_PRI1_INT4
Interrupt 4 Priority Mask
5
8
NVIC_PRI1_INT5
Interrupt 5 Priority Mask
13
16
NVIC_PRI1_INT6
Interrupt 6 Priority Mask
21
24
NVIC_PRI1_INT7
Interrupt 7 Priority Mask
29
32
NVICPRI10
Interrupt 40-43 Priority
0x428
read-write
n
0x0
0x0
NVIC_PRI10_INT40
Interrupt 40 Priority Mask
5
8
NVIC_PRI10_INT41
Interrupt 41 Priority Mask
13
16
NVIC_PRI10_INT42
Interrupt 42 Priority Mask
21
24
NVIC_PRI10_INT43
Interrupt 43 Priority Mask
29
32
NVICPRI11
Interrupt 44-47 Priority
0x42C
read-write
n
0x0
0x0
NVIC_PRI11_INT44
Interrupt 44 Priority Mask
5
8
NVIC_PRI11_INT45
Interrupt 45 Priority Mask
13
16
NVIC_PRI11_INT46
Interrupt 46 Priority Mask
21
24
NVIC_PRI11_INT47
Interrupt 47 Priority Mask
29
32
NVICPRI12
Interrupt 48-51 Priority
0x430
read-write
n
0x0
0x0
NVIC_PRI12_INT48
Interrupt 48 Priority Mask
5
8
NVIC_PRI12_INT49
Interrupt 49 Priority Mask
13
16
NVIC_PRI12_INT50
Interrupt 50 Priority Mask
21
24
NVIC_PRI12_INT51
Interrupt 51 Priority Mask
29
32
NVICPRI13
Interrupt 52-53 Priority
0x434
read-write
n
0x0
0x0
NVIC_PRI13_INT52
Interrupt 52 Priority Mask
5
8
NVIC_PRI13_INT53
Interrupt 53 Priority Mask
13
16
NVIC_PRI13_INT54
Interrupt 54 Priority Mask
21
24
NVIC_PRI13_INT55
Interrupt 55 Priority Mask
29
32
NVICPRI2
Interrupt 8-11 Priority
0x408
read-write
n
0x0
0x0
NVIC_PRI2_INT10
Interrupt 10 Priority Mask
21
24
NVIC_PRI2_INT11
Interrupt 11 Priority Mask
29
32
NVIC_PRI2_INT8
Interrupt 8 Priority Mask
5
8
NVIC_PRI2_INT9
Interrupt 9 Priority Mask
13
16
NVICPRI3
Interrupt 12-15 Priority
0x40C
read-write
n
0x0
0x0
NVIC_PRI3_INT12
Interrupt 12 Priority Mask
5
8
NVIC_PRI3_INT13
Interrupt 13 Priority Mask
13
16
NVIC_PRI3_INT14
Interrupt 14 Priority Mask
21
24
NVIC_PRI3_INT15
Interrupt 15 Priority Mask
29
32
NVICPRI4
Interrupt 16-19 Priority
0x410
read-write
n
0x0
0x0
NVIC_PRI4_INT16
Interrupt 16 Priority Mask
5
8
NVIC_PRI4_INT17
Interrupt 17 Priority Mask
13
16
NVIC_PRI4_INT18
Interrupt 18 Priority Mask
21
24
NVIC_PRI4_INT19
Interrupt 19 Priority Mask
29
32
NVICPRI5
Interrupt 20-23 Priority
0x414
read-write
n
0x0
0x0
NVIC_PRI5_INT20
Interrupt 20 Priority Mask
5
8
NVIC_PRI5_INT21
Interrupt 21 Priority Mask
13
16
NVIC_PRI5_INT22
Interrupt 22 Priority Mask
21
24
NVIC_PRI5_INT23
Interrupt 23 Priority Mask
29
32
NVICPRI6
Interrupt 24-27 Priority
0x418
read-write
n
0x0
0x0
NVIC_PRI6_INT24
Interrupt 24 Priority Mask
5
8
NVIC_PRI6_INT25
Interrupt 25 Priority Mask
13
16
NVIC_PRI6_INT26
Interrupt 26 Priority Mask
21
24
NVIC_PRI6_INT27
Interrupt 27 Priority Mask
29
32
NVICPRI7
Interrupt 28-31 Priority
0x41C
read-write
n
0x0
0x0
NVIC_PRI7_INT28
Interrupt 28 Priority Mask
5
8
NVIC_PRI7_INT29
Interrupt 29 Priority Mask
13
16
NVIC_PRI7_INT30
Interrupt 30 Priority Mask
21
24
NVIC_PRI7_INT31
Interrupt 31 Priority Mask
29
32
NVICPRI8
Interrupt 32-35 Priority
0x420
read-write
n
0x0
0x0
NVIC_PRI8_INT32
Interrupt 32 Priority Mask
5
8
NVIC_PRI8_INT33
Interrupt 33 Priority Mask
13
16
NVIC_PRI8_INT34
Interrupt 34 Priority Mask
21
24
NVIC_PRI8_INT35
Interrupt 35 Priority Mask
29
32
NVICPRI9
Interrupt 36-39 Priority
0x424
read-write
n
0x0
0x0
NVIC_PRI9_INT36
Interrupt 36 Priority Mask
5
8
NVIC_PRI9_INT37
Interrupt 37 Priority Mask
13
16
NVIC_PRI9_INT38
Interrupt 38 Priority Mask
21
24
NVIC_PRI9_INT39
Interrupt 39 Priority Mask
29
32
NVICST_CAL
SysTick Calibration Value Reg
0x1C
read-write
n
0x0
0x0
NVIC_ST_CAL_NOREF
No reference clock
31
32
NVIC_ST_CAL_ONEMS
1ms reference value
0
24
NVIC_ST_CAL_SKEW
Clock skew
30
31
NVICST_CTRL
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
NVIC_ST_CTRL_CLK_SRC
Clock Source
2
3
NVIC_ST_CTRL_COUNT
Count Flag
16
17
NVIC_ST_CTRL_ENABLE
Enable
0
1
NVIC_ST_CTRL_INTEN
Interrupt Enable
1
2
NVICST_CURRENT
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
NVIC_ST_CURRENT
Current Value
0
24
NVICST_RELOAD
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
NVIC_ST_RELOAD
Reload Value
0
24
NVICSW_TRIG
Software Trigger Interrupt
0xF00
write-only
n
0x0
0x0
NVIC_SW_TRIG_INTID
Interrupt ID
0
6
write-only
NVICSYS_CTRL
System Control
0xD10
read-write
n
0x0
0x0
NVIC_SYS_CTRL_SEVONPEND
Wake Up on Pending
4
5
NVIC_SYS_CTRL_SLEEPDEEP
Deep Sleep Enable
2
3
NVIC_SYS_CTRL_SLEEPEXIT
Sleep on ISR Exit
1
2
NVICSYS_HND_CTRL
System Handler Control and State
0xD24
read-write
n
0x0
0x0
NVIC_SYS_HND_CTRL_BUS
Bus Fault Enable
17
18
NVIC_SYS_HND_CTRL_BUSA
Bus Fault Active
1
2
NVIC_SYS_HND_CTRL_BUSP
Bus Fault Pending
14
15
NVIC_SYS_HND_CTRL_MEM
Memory Management Fault Enable
16
17
NVIC_SYS_HND_CTRL_MEMA
Memory Management Fault Active
0
1
NVIC_SYS_HND_CTRL_MEMP
Memory Management Fault Pending
13
14
NVIC_SYS_HND_CTRL_MON
Debug Monitor Active
8
9
NVIC_SYS_HND_CTRL_PNDSV
PendSV Exception Active
10
11
NVIC_SYS_HND_CTRL_SVC
SVC Call Pending
15
16
NVIC_SYS_HND_CTRL_SVCA
SVC Call Active
7
8
NVIC_SYS_HND_CTRL_TICK
SysTick Exception Active
11
12
NVIC_SYS_HND_CTRL_USAGE
Usage Fault Enable
18
19
NVIC_SYS_HND_CTRL_USAGEP
Usage Fault Pending
12
13
NVIC_SYS_HND_CTRL_USGA
Usage Fault Active
3
4
NVICSYS_PRI1
System Handler Priority 1
0xD18
read-write
n
0x0
0x0
NVIC_SYS_PRI1_BUS
Bus Fault Priority
13
16
NVIC_SYS_PRI1_MEM
Memory Management Fault Priority
5
8
NVIC_SYS_PRI1_USAGE
Usage Fault Priority
21
24
NVICSYS_PRI2
System Handler Priority 2
0xD1C
read-write
n
0x0
0x0
NVIC_SYS_PRI2_SVC
SVCall Priority
29
32
NVICSYS_PRI3
System Handler Priority 3
0xD20
read-write
n
0x0
0x0
NVIC_SYS_PRI3_DEBUG
Debug Priority
5
8
NVIC_SYS_PRI3_PENDSV
PendSV Priority
21
24
NVIC_SYS_PRI3_TICK
SysTick Exception Priority
29
32
NVICUNPEND0
Interrupt 0-31 Clear Pending
0x280
read-write
n
0x0
0x0
NVIC_UNPEND0_INT
Interrupt Clear Pending
0
32
NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x1
NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x10
NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x100
NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x1000
NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x10000
NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x100000
NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x1000000
NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x10000000
NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x2
NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x20
NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x200
NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x2000
NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x20000
NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x200000
NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x2000000
NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x20000000
NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x4
NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x40
NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x400
NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x4000
NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x40000
NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x400000
NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x4000000
NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x40000000
NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x8
NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x80
NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x800
NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x8000
NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x80000
NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x800000
NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x8000000
NVIC_UNPEND0_INT31
Interrupt 31 unpend
0x80000000
NVICUNPEND1
Interrupt 32-54 Clear Pending
0x284
read-write
n
0x0
0x0
NVIC_UNPEND1_INT
Interrupt Clear Pending
0
23
NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x1
NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x10
NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x100
NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x1000
NVIC_UNPEND1_INT48
Interrupt 48 unpend
0x10000
NVIC_UNPEND1_INT52
Interrupt 52 unpend
0x100000
NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x2
NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x20
NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x200
NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x2000
NVIC_UNPEND1_INT49
Interrupt 49 unpend
0x20000
NVIC_UNPEND1_INT53
Interrupt 53 unpend
0x200000
NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x4
NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x40
NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x400
NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x4000
NVIC_UNPEND1_INT50
Interrupt 50 unpend
0x40000
NVIC_UNPEND1_INT54
Interrupt 54 unpend
0x400000
NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x8
NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x80
NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x800
NVIC_UNPEND1_INT47
Interrupt 47 unpend
0x8000
NVIC_UNPEND1_INT51
Interrupt 51 unpend
0x80000
NVICVTABLE
Vector Table Offset
0xD08
read-write
n
0x0
0x0
NVIC_VTABLE_BASE
Vector Table Base
29
30
NVIC_VTABLE_OFFSET
Vector Table Offset
9
29
PEND0
Interrupt 0-31 Set Pending
0x200
-1
read-write
n
0x0
0x0
NVIC_PEND0_INT
Interrupt Set Pending
0
32
NVIC_PEND0_INT0
Interrupt 0 pend
0x1
NVIC_PEND0_INT4
Interrupt 4 pend
0x10
NVIC_PEND0_INT8
Interrupt 8 pend
0x100
NVIC_PEND0_INT12
Interrupt 12 pend
0x1000
NVIC_PEND0_INT16
Interrupt 16 pend
0x10000
NVIC_PEND0_INT20
Interrupt 20 pend
0x100000
NVIC_PEND0_INT24
Interrupt 24 pend
0x1000000
NVIC_PEND0_INT28
Interrupt 28 pend
0x10000000
NVIC_PEND0_INT1
Interrupt 1 pend
0x2
NVIC_PEND0_INT5
Interrupt 5 pend
0x20
NVIC_PEND0_INT9
Interrupt 9 pend
0x200
NVIC_PEND0_INT13
Interrupt 13 pend
0x2000
NVIC_PEND0_INT17
Interrupt 17 pend
0x20000
NVIC_PEND0_INT21
Interrupt 21 pend
0x200000
NVIC_PEND0_INT25
Interrupt 25 pend
0x2000000
NVIC_PEND0_INT29
Interrupt 29 pend
0x20000000
NVIC_PEND0_INT2
Interrupt 2 pend
0x4
NVIC_PEND0_INT6
Interrupt 6 pend
0x40
NVIC_PEND0_INT10
Interrupt 10 pend
0x400
NVIC_PEND0_INT14
Interrupt 14 pend
0x4000
NVIC_PEND0_INT18
Interrupt 18 pend
0x40000
NVIC_PEND0_INT22
Interrupt 22 pend
0x400000
NVIC_PEND0_INT26
Interrupt 26 pend
0x4000000
NVIC_PEND0_INT30
Interrupt 30 pend
0x40000000
NVIC_PEND0_INT3
Interrupt 3 pend
0x8
NVIC_PEND0_INT7
Interrupt 7 pend
0x80
NVIC_PEND0_INT11
Interrupt 11 pend
0x800
NVIC_PEND0_INT15
Interrupt 15 pend
0x8000
NVIC_PEND0_INT19
Interrupt 19 pend
0x80000
NVIC_PEND0_INT23
Interrupt 23 pend
0x800000
NVIC_PEND0_INT27
Interrupt 27 pend
0x8000000
NVIC_PEND0_INT31
Interrupt 31 pend
0x80000000
PEND1
Interrupt 32-54 Set Pending
0x204
-1
read-write
n
0x0
0x0
NVIC_PEND1_INT
Interrupt Set Pending
0
23
NVIC_PEND1_INT32
Interrupt 32 pend
0x1
NVIC_PEND1_INT36
Interrupt 36 pend
0x10
NVIC_PEND1_INT40
Interrupt 40 pend
0x100
NVIC_PEND1_INT44
Interrupt 44 pend
0x1000
NVIC_PEND1_INT48
Interrupt 48 pend
0x10000
NVIC_PEND1_INT52
Interrupt 52 pend
0x100000
NVIC_PEND1_INT33
Interrupt 33 pend
0x2
NVIC_PEND1_INT37
Interrupt 37 pend
0x20
NVIC_PEND1_INT41
Interrupt 41 pend
0x200
NVIC_PEND1_INT45
Interrupt 45 pend
0x2000
NVIC_PEND1_INT49
Interrupt 49 pend
0x20000
NVIC_PEND1_INT53
Interrupt 53 pend
0x200000
NVIC_PEND1_INT34
Interrupt 34 pend
0x4
NVIC_PEND1_INT38
Interrupt 38 pend
0x40
NVIC_PEND1_INT42
Interrupt 42 pend
0x400
NVIC_PEND1_INT46
Interrupt 46 pend
0x4000
NVIC_PEND1_INT50
Interrupt 50 pend
0x40000
NVIC_PEND1_INT54
Interrupt 54 pend
0x400000
NVIC_PEND1_INT35
Interrupt 35 pend
0x8
NVIC_PEND1_INT39
Interrupt 39 pend
0x80
NVIC_PEND1_INT43
Interrupt 43 pend
0x800
NVIC_PEND1_INT47
Interrupt 47 pend
0x8000
NVIC_PEND1_INT51
Interrupt 51 pend
0x80000
PRI0
Interrupt 0-3 Priority
0x400
-1
read-write
n
0x0
0x0
NVIC_PRI0_INT0
Interrupt 0 Priority Mask
5
8
NVIC_PRI0_INT1
Interrupt 1 Priority Mask
13
16
NVIC_PRI0_INT2
Interrupt 2 Priority Mask
21
24
NVIC_PRI0_INT3
Interrupt 3 Priority Mask
29
32
PRI1
Interrupt 4-7 Priority
0x404
-1
read-write
n
0x0
0x0
NVIC_PRI1_INT4
Interrupt 4 Priority Mask
5
8
NVIC_PRI1_INT5
Interrupt 5 Priority Mask
13
16
NVIC_PRI1_INT6
Interrupt 6 Priority Mask
21
24
NVIC_PRI1_INT7
Interrupt 7 Priority Mask
29
32
PRI10
Interrupt 40-43 Priority
0x428
-1
read-write
n
0x0
0x0
NVIC_PRI10_INT40
Interrupt 40 Priority Mask
5
8
NVIC_PRI10_INT41
Interrupt 41 Priority Mask
13
16
NVIC_PRI10_INT42
Interrupt 42 Priority Mask
21
24
NVIC_PRI10_INT43
Interrupt 43 Priority Mask
29
32
PRI11
Interrupt 44-47 Priority
0x42C
-1
read-write
n
0x0
0x0
NVIC_PRI11_INT44
Interrupt 44 Priority Mask
5
8
NVIC_PRI11_INT45
Interrupt 45 Priority Mask
13
16
NVIC_PRI11_INT46
Interrupt 46 Priority Mask
21
24
NVIC_PRI11_INT47
Interrupt 47 Priority Mask
29
32
PRI12
Interrupt 48-51 Priority
0x430
-1
read-write
n
0x0
0x0
NVIC_PRI12_INT48
Interrupt 48 Priority Mask
5
8
NVIC_PRI12_INT49
Interrupt 49 Priority Mask
13
16
NVIC_PRI12_INT50
Interrupt 50 Priority Mask
21
24
NVIC_PRI12_INT51
Interrupt 51 Priority Mask
29
32
PRI13
Interrupt 52-53 Priority
0x434
-1
read-write
n
0x0
0x0
NVIC_PRI13_INT52
Interrupt 52 Priority Mask
5
8
NVIC_PRI13_INT53
Interrupt 53 Priority Mask
13
16
NVIC_PRI13_INT54
Interrupt 54 Priority Mask
21
24
NVIC_PRI13_INT55
Interrupt 55 Priority Mask
29
32
PRI2
Interrupt 8-11 Priority
0x408
-1
read-write
n
0x0
0x0
NVIC_PRI2_INT10
Interrupt 10 Priority Mask
21
24
NVIC_PRI2_INT11
Interrupt 11 Priority Mask
29
32
NVIC_PRI2_INT8
Interrupt 8 Priority Mask
5
8
NVIC_PRI2_INT9
Interrupt 9 Priority Mask
13
16
PRI3
Interrupt 12-15 Priority
0x40C
-1
read-write
n
0x0
0x0
NVIC_PRI3_INT12
Interrupt 12 Priority Mask
5
8
NVIC_PRI3_INT13
Interrupt 13 Priority Mask
13
16
NVIC_PRI3_INT14
Interrupt 14 Priority Mask
21
24
NVIC_PRI3_INT15
Interrupt 15 Priority Mask
29
32
PRI4
Interrupt 16-19 Priority
0x410
-1
read-write
n
0x0
0x0
NVIC_PRI4_INT16
Interrupt 16 Priority Mask
5
8
NVIC_PRI4_INT17
Interrupt 17 Priority Mask
13
16
NVIC_PRI4_INT18
Interrupt 18 Priority Mask
21
24
NVIC_PRI4_INT19
Interrupt 19 Priority Mask
29
32
PRI5
Interrupt 20-23 Priority
0x414
-1
read-write
n
0x0
0x0
NVIC_PRI5_INT20
Interrupt 20 Priority Mask
5
8
NVIC_PRI5_INT21
Interrupt 21 Priority Mask
13
16
NVIC_PRI5_INT22
Interrupt 22 Priority Mask
21
24
NVIC_PRI5_INT23
Interrupt 23 Priority Mask
29
32
PRI6
Interrupt 24-27 Priority
0x418
-1
read-write
n
0x0
0x0
NVIC_PRI6_INT24
Interrupt 24 Priority Mask
5
8
NVIC_PRI6_INT25
Interrupt 25 Priority Mask
13
16
NVIC_PRI6_INT26
Interrupt 26 Priority Mask
21
24
NVIC_PRI6_INT27
Interrupt 27 Priority Mask
29
32
PRI7
Interrupt 28-31 Priority
0x41C
-1
read-write
n
0x0
0x0
NVIC_PRI7_INT28
Interrupt 28 Priority Mask
5
8
NVIC_PRI7_INT29
Interrupt 29 Priority Mask
13
16
NVIC_PRI7_INT30
Interrupt 30 Priority Mask
21
24
NVIC_PRI7_INT31
Interrupt 31 Priority Mask
29
32
PRI8
Interrupt 32-35 Priority
0x420
-1
read-write
n
0x0
0x0
NVIC_PRI8_INT32
Interrupt 32 Priority Mask
5
8
NVIC_PRI8_INT33
Interrupt 33 Priority Mask
13
16
NVIC_PRI8_INT34
Interrupt 34 Priority Mask
21
24
NVIC_PRI8_INT35
Interrupt 35 Priority Mask
29
32
PRI9
Interrupt 36-39 Priority
0x424
-1
read-write
n
0x0
0x0
NVIC_PRI9_INT36
Interrupt 36 Priority Mask
5
8
NVIC_PRI9_INT37
Interrupt 37 Priority Mask
13
16
NVIC_PRI9_INT38
Interrupt 38 Priority Mask
21
24
NVIC_PRI9_INT39
Interrupt 39 Priority Mask
29
32
ST_CAL
SysTick Calibration Value Reg
0x1C
-1
read-write
n
0x0
0x0
NVIC_ST_CAL_NOREF
No reference clock
31
32
NVIC_ST_CAL_ONEMS
1ms reference value
0
24
NVIC_ST_CAL_SKEW
Clock skew
30
31
ST_CTRL
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
NVIC_ST_CTRL_CLK_SRC
Clock Source
2
3
NVIC_ST_CTRL_COUNT
Count Flag
16
17
NVIC_ST_CTRL_ENABLE
Enable
0
1
NVIC_ST_CTRL_INTEN
Interrupt Enable
1
2
ST_CURRENT
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
NVIC_ST_CURRENT
Current Value
0
24
ST_RELOAD
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
NVIC_ST_RELOAD
Reload Value
0
24
SW_TRIG
Software Trigger Interrupt
0xF00
-1
write-only
n
0x0
0x0
NVIC_SW_TRIG_INTID
Interrupt ID
0
6
write-only
SYS_CTRL
System Control
0xD10
-1
read-write
n
0x0
0x0
NVIC_SYS_CTRL_SEVONPEND
Wake Up on Pending
4
5
NVIC_SYS_CTRL_SLEEPDEEP
Deep Sleep Enable
2
3
NVIC_SYS_CTRL_SLEEPEXIT
Sleep on ISR Exit
1
2
SYS_HND_CTRL
System Handler Control and State
0xD24
-1
read-write
n
0x0
0x0
NVIC_SYS_HND_CTRL_BUS
Bus Fault Enable
17
18
NVIC_SYS_HND_CTRL_BUSA
Bus Fault Active
1
2
NVIC_SYS_HND_CTRL_BUSP
Bus Fault Pending
14
15
NVIC_SYS_HND_CTRL_MEM
Memory Management Fault Enable
16
17
NVIC_SYS_HND_CTRL_MEMA
Memory Management Fault Active
0
1
NVIC_SYS_HND_CTRL_MEMP
Memory Management Fault Pending
13
14
NVIC_SYS_HND_CTRL_MON
Debug Monitor Active
8
9
NVIC_SYS_HND_CTRL_PNDSV
PendSV Exception Active
10
11
NVIC_SYS_HND_CTRL_SVC
SVC Call Pending
15
16
NVIC_SYS_HND_CTRL_SVCA
SVC Call Active
7
8
NVIC_SYS_HND_CTRL_TICK
SysTick Exception Active
11
12
NVIC_SYS_HND_CTRL_USAGE
Usage Fault Enable
18
19
NVIC_SYS_HND_CTRL_USAGEP
Usage Fault Pending
12
13
NVIC_SYS_HND_CTRL_USGA
Usage Fault Active
3
4
SYS_PRI1
System Handler Priority 1
0xD18
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI1_BUS
Bus Fault Priority
13
16
NVIC_SYS_PRI1_MEM
Memory Management Fault Priority
5
8
NVIC_SYS_PRI1_USAGE
Usage Fault Priority
21
24
SYS_PRI2
System Handler Priority 2
0xD1C
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI2_SVC
SVCall Priority
29
32
SYS_PRI3
System Handler Priority 3
0xD20
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI3_DEBUG
Debug Priority
5
8
NVIC_SYS_PRI3_PENDSV
PendSV Priority
21
24
NVIC_SYS_PRI3_TICK
SysTick Exception Priority
29
32
UNPEND0
Interrupt 0-31 Clear Pending
0x280
-1
read-write
n
0x0
0x0
NVIC_UNPEND0_INT
Interrupt Clear Pending
0
32
NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x1
NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x10
NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x100
NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x1000
NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x10000
NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x100000
NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x1000000
NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x10000000
NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x2
NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x20
NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x200
NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x2000
NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x20000
NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x200000
NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x2000000
NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x20000000
NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x4
NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x40
NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x400
NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x4000
NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x40000
NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x400000
NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x4000000
NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x40000000
NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x8
NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x80
NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x800
NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x8000
NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x80000
NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x800000
NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x8000000
NVIC_UNPEND0_INT31
Interrupt 31 unpend
0x80000000
UNPEND1
Interrupt 32-54 Clear Pending
0x284
-1
read-write
n
0x0
0x0
NVIC_UNPEND1_INT
Interrupt Clear Pending
0
23
NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x1
NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x10
NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x100
NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x1000
NVIC_UNPEND1_INT48
Interrupt 48 unpend
0x10000
NVIC_UNPEND1_INT52
Interrupt 52 unpend
0x100000
NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x2
NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x20
NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x200
NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x2000
NVIC_UNPEND1_INT49
Interrupt 49 unpend
0x20000
NVIC_UNPEND1_INT53
Interrupt 53 unpend
0x200000
NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x4
NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x40
NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x400
NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x4000
NVIC_UNPEND1_INT50
Interrupt 50 unpend
0x40000
NVIC_UNPEND1_INT54
Interrupt 54 unpend
0x400000
NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x8
NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x80
NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x800
NVIC_UNPEND1_INT47
Interrupt 47 unpend
0x8000
NVIC_UNPEND1_INT51
Interrupt 51 unpend
0x80000
VTABLE
Vector Table Offset
0xD08
-1
read-write
n
0x0
0x0
NVIC_VTABLE_BASE
Vector Table Base
29
30
NVIC_VTABLE_OFFSET
Vector Table Offset
9
29
PWM0
Register map for PWM0 peripheral
PWM
0x0
0x0
0x1000
registers
n
0_CMPA
PWM0 Compare A
0x58
read-write
n
0x0
0x0
PWM_X_CMPA
Comparator A Value
0
16
0_CMPB
PWM0 Compare B
0x5C
read-write
n
0x0
0x0
PWM_X_CMPB
Comparator B Value
0
16
0_COUNT
PWM0 Counter
0x54
read-write
n
0x0
0x0
PWM_X_COUNT
Counter Value
0
16
0_CTL
PWM0 Control
0x40
read-write
n
0x0
0x0
PWM_X_CTL_CMPAUPD
Comparator A Update Mode
4
5
PWM_X_CTL_CMPBUPD
Comparator B Update Mode
5
6
PWM_X_CTL_DBCTLUPD
PWMnDBCTL Update Mode
10
12
PWM_X_CTL_DBCTLUPD_I
Immediate
0x0
PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBFALLUPD
PWMnDBFALL Update Mode
14
16
PWM_X_CTL_DBFALLUPD_I
Immediate
0x0
PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBRISEUPD
PWMnDBRISE Update Mode
12
14
PWM_X_CTL_DBRISEUPD_I
Immediate
0x0
PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DEBUG
Debug Mode
2
3
PWM_X_CTL_ENABLE
PWM Block Enable
0
1
PWM_X_CTL_FLTSRC
Fault Condition Source
16
17
PWM_X_CTL_GENAUPD
PWMnGENA Update Mode
6
8
PWM_X_CTL_GENAUPD_I
Immediate
0x0
PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENAUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_GENBUPD
PWMnGENB Update Mode
8
10
PWM_X_CTL_GENBUPD_I
Immediate
0x0
PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENBUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_LATCH
Latch Fault Input
18
19
PWM_X_CTL_LOADUPD
Load Register Update Mode
3
4
PWM_X_CTL_MINFLTPER
Minimum Fault Period
17
18
PWM_X_CTL_MODE
Counter Mode
1
2
0_DBCTL
PWM0 Dead-Band Control
0x68
read-write
n
0x0
0x0
PWM_X_DBCTL_ENABLE
Dead-Band Generator Enable
0
1
0_DBFALL
PWM0 Dead-Band Falling-Edge-Delay
0x70
read-write
n
0x0
0x0
PWM_X_DBFALL_DELAY
Dead-Band Fall Delay
0
12
0_DBRISE
PWM0 Dead-Band Rising-Edge Delay
0x6C
read-write
n
0x0
0x0
PWM_X_DBRISE_DELAY
Dead-Band Rise Delay
0
12
0_FLTSEN
PWM0 Fault Pin Logic Sense
0x800
read-write
n
0x0
0x0
PWM_X_FLTSEN_FAULT0
Fault0 Sense
0
1
PWM_X_FLTSEN_FAULT1
Fault1 Sense
1
2
PWM_X_FLTSEN_FAULT2
Fault2 Sense
2
3
PWM_X_FLTSEN_FAULT3
Fault3 Sense
3
4
0_FLTSRC0
PWM0 Fault Source 0
0x74
read-write
n
0x0
0x0
PWM_X_FLTSRC0_FAULT0
Fault0 Input
0
1
PWM_X_FLTSRC0_FAULT1
Fault1 Input
1
2
PWM_X_FLTSRC0_FAULT2
Fault2 Input
2
3
PWM_X_FLTSRC0_FAULT3
Fault3 Input
3
4
0_FLTSRC1
PWM0 Fault Source 1
0x78
read-write
n
0x0
0x0
PWM_X_FLTSRC1_DCMP0
Digital Comparator 0
0
1
PWM_X_FLTSRC1_DCMP1
Digital Comparator 1
1
2
PWM_X_FLTSRC1_DCMP2
Digital Comparator 2
2
3
PWM_X_FLTSRC1_DCMP3
Digital Comparator 3
3
4
PWM_X_FLTSRC1_DCMP4
Digital Comparator 4
4
5
PWM_X_FLTSRC1_DCMP5
Digital Comparator 5
5
6
PWM_X_FLTSRC1_DCMP6
Digital Comparator 6
6
7
PWM_X_FLTSRC1_DCMP7
Digital Comparator 7
7
8
0_FLTSTAT0
PWM0 Fault Status 0
0x804
read-only
n
0x0
0x0
PWM_X_FLTSTAT0_FAULT0
Fault Input 0
0
1
read-only
PWM_X_FLTSTAT0_FAULT1
Fault Input 1
1
2
read-only
PWM_X_FLTSTAT0_FAULT2
Fault Input 2
2
3
read-only
PWM_X_FLTSTAT0_FAULT3
Fault Input 3
3
4
read-only
0_FLTSTAT1
PWM0 Fault Status 1
0x808
read-only
n
0x0
0x0
PWM_X_FLTSTAT1_DCMP0
Digital Comparator 0 Trigger
0
1
read-only
PWM_X_FLTSTAT1_DCMP1
Digital Comparator 1 Trigger
1
2
read-only
PWM_X_FLTSTAT1_DCMP2
Digital Comparator 2 Trigger
2
3
read-only
PWM_X_FLTSTAT1_DCMP3
Digital Comparator 3 Trigger
3
4
read-only
PWM_X_FLTSTAT1_DCMP4
Digital Comparator 4 Trigger
4
5
read-only
PWM_X_FLTSTAT1_DCMP5
Digital Comparator 5 Trigger
5
6
read-only
PWM_X_FLTSTAT1_DCMP6
Digital Comparator 6 Trigger
6
7
read-only
PWM_X_FLTSTAT1_DCMP7
Digital Comparator 7 Trigger
7
8
read-only
0_GENA
PWM0 Generator A Control
0x60
read-write
n
0x0
0x0
PWM_X_GENA_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTZERO
Action for Counter=0
0
2
PWM_X_GENA_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x1
PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
0x3
0_GENB
PWM0 Generator B Control
0x64
read-write
n
0x0
0x0
PWM_X_GENB_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTZERO
Action for Counter=0
0
2
PWM_X_GENB_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x1
PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
0x3
0_INTEN
PWM0 Interrupt and Trigger Enable
0x44
read-write
n
0x0
0x0
PWM_X_INTEN_INTCMPAD
Interrupt for Counter=PWMnCMPA Down
3
4
PWM_X_INTEN_INTCMPAU
Interrupt for Counter=PWMnCMPA Up
2
3
PWM_X_INTEN_INTCMPBD
Interrupt for Counter=PWMnCMPB Down
5
6
PWM_X_INTEN_INTCMPBU
Interrupt for Counter=PWMnCMPB Up
4
5
PWM_X_INTEN_INTCNTLOAD
Interrupt for Counter=PWMnLOAD
1
2
PWM_X_INTEN_INTCNTZERO
Interrupt for Counter=0
0
1
PWM_X_INTEN_TRCMPAD
Trigger for Counter=PWMnCMPA Down
11
12
PWM_X_INTEN_TRCMPAU
Trigger for Counter=PWMnCMPA Up
10
11
PWM_X_INTEN_TRCMPBD
Trigger for Counter=PWMnCMPB Down
13
14
PWM_X_INTEN_TRCMPBU
Trigger for Counter=PWMnCMPB Up
12
13
PWM_X_INTEN_TRCNTLOAD
Trigger for Counter=PWMnLOAD
9
10
PWM_X_INTEN_TRCNTZERO
Trigger for Counter=0
8
9
0_ISC
PWM0 Interrupt Status and Clear
0x4C
read-write
n
0x0
0x0
PWM_X_ISC_INTCMPAD
Comparator A Down Interrupt
3
4
PWM_X_ISC_INTCMPAU
Comparator A Up Interrupt
2
3
PWM_X_ISC_INTCMPBD
Comparator B Down Interrupt
5
6
PWM_X_ISC_INTCMPBU
Comparator B Up Interrupt
4
5
PWM_X_ISC_INTCNTLOAD
Counter=Load Interrupt
1
2
PWM_X_ISC_INTCNTZERO
Counter=0 Interrupt
0
1
0_LOAD
PWM0 Load
0x50
read-write
n
0x0
0x0
PWM_X_LOAD
Counter Load Value
0
16
0_MINFLTPER
PWM0 Minimum Fault Period
0x7C
read-write
n
0x0
0x0
PWM_X_MINFLTPER
Minimum Fault Period
0
16
0_RIS
PWM0 Raw Interrupt Status
0x48
read-write
n
0x0
0x0
PWM_X_RIS_INTCMPAD
Comparator A Down Interrupt Status
3
4
PWM_X_RIS_INTCMPAU
Comparator A Up Interrupt Status
2
3
PWM_X_RIS_INTCMPBD
Comparator B Down Interrupt Status
5
6
PWM_X_RIS_INTCMPBU
Comparator B Up Interrupt Status
4
5
PWM_X_RIS_INTCNTLOAD
Counter=Load Interrupt Status
1
2
PWM_X_RIS_INTCNTZERO
Counter=0 Interrupt Status
0
1
1_CMPA
PWM1 Compare A
0x98
read-write
n
0x0
0x0
1_CMPB
PWM1 Compare B
0x9C
read-write
n
0x0
0x0
1_COUNT
PWM1 Counter
0x94
read-write
n
0x0
0x0
1_CTL
PWM1 Control
0x80
read-write
n
0x0
0x0
1_DBCTL
PWM1 Dead-Band Control
0xA8
read-write
n
0x0
0x0
1_DBFALL
PWM1 Dead-Band Falling-Edge-Delay
0xB0
read-write
n
0x0
0x0
1_DBRISE
PWM1 Dead-Band Rising-Edge Delay
0xAC
read-write
n
0x0
0x0
1_FLTSEN
PWM1 Fault Pin Logic Sense
0x880
read-write
n
0x0
0x0
1_FLTSRC0
PWM1 Fault Source 0
0xB4
read-write
n
0x0
0x0
1_FLTSRC1
PWM1 Fault Source 1
0xB8
read-write
n
0x0
0x0
1_FLTSTAT0
PWM1 Fault Status 0
0x884
read-only
n
0x0
0x0
1_FLTSTAT1
PWM1 Fault Status 1
0x888
read-only
n
0x0
0x0
1_GENA
PWM1 Generator A Control
0xA0
read-write
n
0x0
0x0
1_GENB
PWM1 Generator B Control
0xA4
read-write
n
0x0
0x0
1_INTEN
PWM1 Interrupt and Trigger Enable
0x84
read-write
n
0x0
0x0
1_ISC
PWM1 Interrupt Status and Clear
0x8C
read-write
n
0x0
0x0
1_LOAD
PWM1 Load
0x90
read-write
n
0x0
0x0
1_MINFLTPER
PWM1 Minimum Fault Period
0xBC
read-write
n
0x0
0x0
1_RIS
PWM1 Raw Interrupt Status
0x88
read-write
n
0x0
0x0
2_CMPA
PWM2 Compare A
0xD8
read-write
n
0x0
0x0
2_CMPB
PWM2 Compare B
0xDC
read-write
n
0x0
0x0
2_COUNT
PWM2 Counter
0xD4
read-write
n
0x0
0x0
2_CTL
PWM2 Control
0xC0
read-write
n
0x0
0x0
2_DBCTL
PWM2 Dead-Band Control
0xE8
read-write
n
0x0
0x0
2_DBFALL
PWM2 Dead-Band Falling-Edge-Delay
0xF0
read-write
n
0x0
0x0
2_DBRISE
PWM2 Dead-Band Rising-Edge Delay
0xEC
read-write
n
0x0
0x0
2_FLTSEN
PWM2 Fault Pin Logic Sense
0x900
read-write
n
0x0
0x0
2_FLTSRC0
PWM2 Fault Source 0
0xF4
read-write
n
0x0
0x0
2_FLTSRC1
PWM2 Fault Source 1
0xF8
read-write
n
0x0
0x0
2_FLTSTAT0
PWM2 Fault Status 0
0x904
read-only
n
0x0
0x0
2_FLTSTAT1
PWM2 Fault Status 1
0x908
read-only
n
0x0
0x0
2_GENA
PWM2 Generator A Control
0xE0
read-write
n
0x0
0x0
2_GENB
PWM2 Generator B Control
0xE4
read-write
n
0x0
0x0
2_INTEN
PWM2 Interrupt and Trigger Enable
0xC4
read-write
n
0x0
0x0
2_ISC
PWM2 Interrupt Status and Clear
0xCC
read-write
n
0x0
0x0
2_LOAD
PWM2 Load
0xD0
read-write
n
0x0
0x0
2_MINFLTPER
PWM2 Minimum Fault Period
0xFC
read-write
n
0x0
0x0
2_RIS
PWM2 Raw Interrupt Status
0xC8
read-write
n
0x0
0x0
3_FLTSEN
PWM3 Fault Pin Logic Sense
0x980
read-write
n
0x0
0x0
CTL
PWM Master Control
0x0
-1
read-write
n
0x0
0x0
PWM_CTL_GLOBALSYNC0
Update PWM Generator 0
0
1
PWM_CTL_GLOBALSYNC1
Update PWM Generator 1
1
2
PWM_CTL_GLOBALSYNC2
Update PWM Generator 2
2
3
ENABLE
PWM Output Enable
0x8
-1
read-write
n
0x0
0x0
PWM_ENABLE_PWM0EN
PWM0 Output Enable
0
1
PWM_ENABLE_PWM1EN
PWM1 Output Enable
1
2
PWM_ENABLE_PWM2EN
PWM2 Output Enable
2
3
PWM_ENABLE_PWM3EN
PWM3 Output Enable
3
4
PWM_ENABLE_PWM4EN
PWM4 Output Enable
4
5
PWM_ENABLE_PWM5EN
PWM5 Output Enable
5
6
ENUPD
PWM Enable Update
0x28
-1
read-write
n
0x0
0x0
PWM_ENUPD_ENUPD0
PWM0 Enable Update Mode
0
2
PWM_ENUPD_ENUPD0_IMM
Immediate
0x0
PWM_ENUPD_ENUPD0_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD0_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD1
PWM1 Enable Update Mode
2
4
PWM_ENUPD_ENUPD1_IMM
Immediate
0x0
PWM_ENUPD_ENUPD1_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD1_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD2
PWM2 Enable Update Mode
4
6
PWM_ENUPD_ENUPD2_IMM
Immediate
0x0
PWM_ENUPD_ENUPD2_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD2_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD3
PWM3 Enable Update Mode
6
8
PWM_ENUPD_ENUPD3_IMM
Immediate
0x0
PWM_ENUPD_ENUPD3_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD3_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD4
PWM4 Enable Update Mode
8
10
PWM_ENUPD_ENUPD4_IMM
Immediate
0x0
PWM_ENUPD_ENUPD4_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD4_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD5
PWM5 Enable Update Mode
10
12
PWM_ENUPD_ENUPD5_IMM
Immediate
0x0
PWM_ENUPD_ENUPD5_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD5_GSYNC
Globally Synchronized
0x3
FAULT
PWM Output Fault
0x10
-1
read-write
n
0x0
0x0
PWM_FAULT_FAULT0
PWM0 Fault
0
1
PWM_FAULT_FAULT1
PWM1 Fault
1
2
PWM_FAULT_FAULT2
PWM2 Fault
2
3
PWM_FAULT_FAULT3
PWM3 Fault
3
4
PWM_FAULT_FAULT4
PWM4 Fault
4
5
PWM_FAULT_FAULT5
PWM5 Fault
5
6
FAULTVAL
PWM Fault Condition Value
0x24
-1
read-write
n
0x0
0x0
PWM_FAULTVAL_PWM0
PWM0 Fault Value
0
1
PWM_FAULTVAL_PWM1
PWM1 Fault Value
1
2
PWM_FAULTVAL_PWM2
PWM2 Fault Value
2
3
PWM_FAULTVAL_PWM3
PWM3 Fault Value
3
4
PWM_FAULTVAL_PWM4
PWM4 Fault Value
4
5
PWM_FAULTVAL_PWM5
PWM5 Fault Value
5
6
INTEN
PWM Interrupt Enable
0x14
-1
read-write
n
0x0
0x0
PWM_INTEN_INTFAULT0
Interrupt Fault 0
16
17
PWM_INTEN_INTFAULT1
Interrupt Fault 1
17
18
PWM_INTEN_INTFAULT2
Interrupt Fault 2
18
19
PWM_INTEN_INTFAULT3
Interrupt Fault 3
19
20
PWM_INTEN_INTPWM0
PWM0 Interrupt Enable
0
1
PWM_INTEN_INTPWM1
PWM1 Interrupt Enable
1
2
PWM_INTEN_INTPWM2
PWM2 Interrupt Enable
2
3
INVERT
PWM Output Inversion
0xC
-1
read-write
n
0x0
0x0
PWM_INVERT_PWM0INV
Invert PWM0 Signal
0
1
PWM_INVERT_PWM1INV
Invert PWM1 Signal
1
2
PWM_INVERT_PWM2INV
Invert PWM2 Signal
2
3
PWM_INVERT_PWM3INV
Invert PWM3 Signal
3
4
PWM_INVERT_PWM4INV
Invert PWM4 Signal
4
5
PWM_INVERT_PWM5INV
Invert PWM5 Signal
5
6
ISC
PWM Interrupt Status and Clear
0x1C
-1
read-write
n
0x0
0x0
PWM_ISC_INTFAULT0
FAULT0 Interrupt Asserted
16
17
PWM_ISC_INTFAULT1
FAULT1 Interrupt Asserted
17
18
PWM_ISC_INTFAULT2
FAULT2 Interrupt Asserted
18
19
PWM_ISC_INTFAULT3
FAULT3 Interrupt Asserted
19
20
PWM_ISC_INTPWM0
PWM0 Interrupt Status
0
1
PWM_ISC_INTPWM1
PWM1 Interrupt Status
1
2
PWM_ISC_INTPWM2
PWM2 Interrupt Status
2
3
PWM0CTL
PWM Master Control
0x0
read-write
n
0x0
0x0
PWM_CTL_GLOBALSYNC0
Update PWM Generator 0
0
1
PWM_CTL_GLOBALSYNC1
Update PWM Generator 1
1
2
PWM_CTL_GLOBALSYNC2
Update PWM Generator 2
2
3
PWM0ENABLE
PWM Output Enable
0x8
read-write
n
0x0
0x0
PWM_ENABLE_PWM0EN
PWM0 Output Enable
0
1
PWM_ENABLE_PWM1EN
PWM1 Output Enable
1
2
PWM_ENABLE_PWM2EN
PWM2 Output Enable
2
3
PWM_ENABLE_PWM3EN
PWM3 Output Enable
3
4
PWM_ENABLE_PWM4EN
PWM4 Output Enable
4
5
PWM_ENABLE_PWM5EN
PWM5 Output Enable
5
6
PWM0ENUPD
PWM Enable Update
0x28
read-write
n
0x0
0x0
PWM_ENUPD_ENUPD0
PWM0 Enable Update Mode
0
2
PWM_ENUPD_ENUPD0_IMM
Immediate
0x0
PWM_ENUPD_ENUPD0_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD0_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD1
PWM1 Enable Update Mode
2
4
PWM_ENUPD_ENUPD1_IMM
Immediate
0x0
PWM_ENUPD_ENUPD1_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD1_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD2
PWM2 Enable Update Mode
4
6
PWM_ENUPD_ENUPD2_IMM
Immediate
0x0
PWM_ENUPD_ENUPD2_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD2_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD3
PWM3 Enable Update Mode
6
8
PWM_ENUPD_ENUPD3_IMM
Immediate
0x0
PWM_ENUPD_ENUPD3_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD3_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD4
PWM4 Enable Update Mode
8
10
PWM_ENUPD_ENUPD4_IMM
Immediate
0x0
PWM_ENUPD_ENUPD4_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD4_GSYNC
Globally Synchronized
0x3
PWM_ENUPD_ENUPD5
PWM5 Enable Update Mode
10
12
PWM_ENUPD_ENUPD5_IMM
Immediate
0x0
PWM_ENUPD_ENUPD5_LSYNC
Locally Synchronized
0x2
PWM_ENUPD_ENUPD5_GSYNC
Globally Synchronized
0x3
PWM0FAULT
PWM Output Fault
0x10
read-write
n
0x0
0x0
PWM_FAULT_FAULT0
PWM0 Fault
0
1
PWM_FAULT_FAULT1
PWM1 Fault
1
2
PWM_FAULT_FAULT2
PWM2 Fault
2
3
PWM_FAULT_FAULT3
PWM3 Fault
3
4
PWM_FAULT_FAULT4
PWM4 Fault
4
5
PWM_FAULT_FAULT5
PWM5 Fault
5
6
PWM0FAULTVAL
PWM Fault Condition Value
0x24
read-write
n
0x0
0x0
PWM_FAULTVAL_PWM0
PWM0 Fault Value
0
1
PWM_FAULTVAL_PWM1
PWM1 Fault Value
1
2
PWM_FAULTVAL_PWM2
PWM2 Fault Value
2
3
PWM_FAULTVAL_PWM3
PWM3 Fault Value
3
4
PWM_FAULTVAL_PWM4
PWM4 Fault Value
4
5
PWM_FAULTVAL_PWM5
PWM5 Fault Value
5
6
PWM0INTEN
PWM Interrupt Enable
0x14
read-write
n
0x0
0x0
PWM_INTEN_INTFAULT0
Interrupt Fault 0
16
17
PWM_INTEN_INTFAULT1
Interrupt Fault 1
17
18
PWM_INTEN_INTFAULT2
Interrupt Fault 2
18
19
PWM_INTEN_INTFAULT3
Interrupt Fault 3
19
20
PWM_INTEN_INTPWM0
PWM0 Interrupt Enable
0
1
PWM_INTEN_INTPWM1
PWM1 Interrupt Enable
1
2
PWM_INTEN_INTPWM2
PWM2 Interrupt Enable
2
3
PWM0INVERT
PWM Output Inversion
0xC
read-write
n
0x0
0x0
PWM_INVERT_PWM0INV
Invert PWM0 Signal
0
1
PWM_INVERT_PWM1INV
Invert PWM1 Signal
1
2
PWM_INVERT_PWM2INV
Invert PWM2 Signal
2
3
PWM_INVERT_PWM3INV
Invert PWM3 Signal
3
4
PWM_INVERT_PWM4INV
Invert PWM4 Signal
4
5
PWM_INVERT_PWM5INV
Invert PWM5 Signal
5
6
PWM0ISC
PWM Interrupt Status and Clear
0x1C
read-write
n
0x0
0x0
PWM_ISC_INTFAULT0
FAULT0 Interrupt Asserted
16
17
PWM_ISC_INTFAULT1
FAULT1 Interrupt Asserted
17
18
PWM_ISC_INTFAULT2
FAULT2 Interrupt Asserted
18
19
PWM_ISC_INTFAULT3
FAULT3 Interrupt Asserted
19
20
PWM_ISC_INTPWM0
PWM0 Interrupt Status
0
1
PWM_ISC_INTPWM1
PWM1 Interrupt Status
1
2
PWM_ISC_INTPWM2
PWM2 Interrupt Status
2
3
PWM0RIS
PWM Raw Interrupt Status
0x18
read-write
n
0x0
0x0
PWM_RIS_INTFAULT0
Interrupt Fault PWM 0
16
17
PWM_RIS_INTFAULT1
Interrupt Fault PWM 1
17
18
PWM_RIS_INTFAULT2
Interrupt Fault PWM 2
18
19
PWM_RIS_INTFAULT3
Interrupt Fault PWM 3
19
20
PWM_RIS_INTPWM0
PWM0 Interrupt Asserted
0
1
PWM_RIS_INTPWM1
PWM1 Interrupt Asserted
1
2
PWM_RIS_INTPWM2
PWM2 Interrupt Asserted
2
3
PWM0STATUS
PWM Status
0x20
read-write
n
0x0
0x0
PWM_STATUS_FAULT0
Generator 0 Fault Status
0
1
PWM_STATUS_FAULT1
Generator 1 Fault Status
1
2
PWM_STATUS_FAULT2
Generator 2 Fault Status
2
3
PWM_STATUS_FAULT3
Generator 3 Fault Status
3
4
PWM0SYNC
PWM Time Base Sync
0x4
read-write
n
0x0
0x0
PWM_SYNC_SYNC0
Reset Generator 0 Counter
0
1
PWM_SYNC_SYNC1
Reset Generator 1 Counter
1
2
PWM_SYNC_SYNC2
Reset Generator 2 Counter
2
3
RIS
PWM Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
PWM_RIS_INTFAULT0
Interrupt Fault PWM 0
16
17
PWM_RIS_INTFAULT1
Interrupt Fault PWM 1
17
18
PWM_RIS_INTFAULT2
Interrupt Fault PWM 2
18
19
PWM_RIS_INTFAULT3
Interrupt Fault PWM 3
19
20
PWM_RIS_INTPWM0
PWM0 Interrupt Asserted
0
1
PWM_RIS_INTPWM1
PWM1 Interrupt Asserted
1
2
PWM_RIS_INTPWM2
PWM2 Interrupt Asserted
2
3
STATUS
PWM Status
0x20
-1
read-write
n
0x0
0x0
PWM_STATUS_FAULT0
Generator 0 Fault Status
0
1
PWM_STATUS_FAULT1
Generator 1 Fault Status
1
2
PWM_STATUS_FAULT2
Generator 2 Fault Status
2
3
PWM_STATUS_FAULT3
Generator 3 Fault Status
3
4
SYNC
PWM Time Base Sync
0x4
-1
read-write
n
0x0
0x0
PWM_SYNC_SYNC0
Reset Generator 0 Counter
0
1
PWM_SYNC_SYNC1
Reset Generator 1 Counter
1
2
PWM_SYNC_SYNC2
Reset Generator 2 Counter
2
3
_0_CMPA
PWM0 Compare A
0x58
-1
read-write
n
0x0
0x0
PWM_X_CMPA
Comparator A Value
0
16
_0_CMPB
PWM0 Compare B
0x5C
-1
read-write
n
0x0
0x0
PWM_X_CMPB
Comparator B Value
0
16
_0_COUNT
PWM0 Counter
0x54
-1
read-write
n
0x0
0x0
PWM_X_COUNT
Counter Value
0
16
_0_CTL
PWM0 Control
0x40
-1
read-write
n
0x0
0x0
PWM_X_CTL_CMPAUPD
Comparator A Update Mode
4
5
PWM_X_CTL_CMPBUPD
Comparator B Update Mode
5
6
PWM_X_CTL_DBCTLUPD
PWMnDBCTL Update Mode
10
12
PWM_X_CTL_DBCTLUPD_I
Immediate
0x0
PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBFALLUPD
PWMnDBFALL Update Mode
14
16
PWM_X_CTL_DBFALLUPD_I
Immediate
0x0
PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBRISEUPD
PWMnDBRISE Update Mode
12
14
PWM_X_CTL_DBRISEUPD_I
Immediate
0x0
PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DEBUG
Debug Mode
2
3
PWM_X_CTL_ENABLE
PWM Block Enable
0
1
PWM_X_CTL_FLTSRC
Fault Condition Source
16
17
PWM_X_CTL_GENAUPD
PWMnGENA Update Mode
6
8
PWM_X_CTL_GENAUPD_I
Immediate
0x0
PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENAUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_GENBUPD
PWMnGENB Update Mode
8
10
PWM_X_CTL_GENBUPD_I
Immediate
0x0
PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENBUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_LATCH
Latch Fault Input
18
19
PWM_X_CTL_LOADUPD
Load Register Update Mode
3
4
PWM_X_CTL_MINFLTPER
Minimum Fault Period
17
18
PWM_X_CTL_MODE
Counter Mode
1
2
_0_DBCTL
PWM0 Dead-Band Control
0x68
-1
read-write
n
0x0
0x0
PWM_X_DBCTL_ENABLE
Dead-Band Generator Enable
0
1
_0_DBFALL
PWM0 Dead-Band Falling-Edge-Delay
0x70
-1
read-write
n
0x0
0x0
PWM_X_DBFALL_DELAY
Dead-Band Fall Delay
0
12
_0_DBRISE
PWM0 Dead-Band Rising-Edge Delay
0x6C
-1
read-write
n
0x0
0x0
PWM_X_DBRISE_DELAY
Dead-Band Rise Delay
0
12
_0_FLTSEN
PWM0 Fault Pin Logic Sense
0x800
-1
read-write
n
0x0
0x0
PWM_X_FLTSEN_FAULT0
Fault0 Sense
0
1
PWM_X_FLTSEN_FAULT1
Fault1 Sense
1
2
PWM_X_FLTSEN_FAULT2
Fault2 Sense
2
3
PWM_X_FLTSEN_FAULT3
Fault3 Sense
3
4
_0_FLTSRC0
PWM0 Fault Source 0
0x74
-1
read-write
n
0x0
0x0
PWM_X_FLTSRC0_FAULT0
Fault0 Input
0
1
PWM_X_FLTSRC0_FAULT1
Fault1 Input
1
2
PWM_X_FLTSRC0_FAULT2
Fault2 Input
2
3
PWM_X_FLTSRC0_FAULT3
Fault3 Input
3
4
_0_FLTSRC1
PWM0 Fault Source 1
0x78
-1
read-write
n
0x0
0x0
PWM_X_FLTSRC1_DCMP0
Digital Comparator 0
0
1
PWM_X_FLTSRC1_DCMP1
Digital Comparator 1
1
2
PWM_X_FLTSRC1_DCMP2
Digital Comparator 2
2
3
PWM_X_FLTSRC1_DCMP3
Digital Comparator 3
3
4
PWM_X_FLTSRC1_DCMP4
Digital Comparator 4
4
5
PWM_X_FLTSRC1_DCMP5
Digital Comparator 5
5
6
PWM_X_FLTSRC1_DCMP6
Digital Comparator 6
6
7
PWM_X_FLTSRC1_DCMP7
Digital Comparator 7
7
8
_0_FLTSTAT0
PWM0 Fault Status 0
0x804
-1
read-only
n
0x0
0x0
PWM_X_FLTSTAT0_FAULT0
Fault Input 0
0
1
read-only
PWM_X_FLTSTAT0_FAULT1
Fault Input 1
1
2
read-only
PWM_X_FLTSTAT0_FAULT2
Fault Input 2
2
3
read-only
PWM_X_FLTSTAT0_FAULT3
Fault Input 3
3
4
read-only
_0_FLTSTAT1
PWM0 Fault Status 1
0x808
-1
read-only
n
0x0
0x0
PWM_X_FLTSTAT1_DCMP0
Digital Comparator 0 Trigger
0
1
read-only
PWM_X_FLTSTAT1_DCMP1
Digital Comparator 1 Trigger
1
2
read-only
PWM_X_FLTSTAT1_DCMP2
Digital Comparator 2 Trigger
2
3
read-only
PWM_X_FLTSTAT1_DCMP3
Digital Comparator 3 Trigger
3
4
read-only
PWM_X_FLTSTAT1_DCMP4
Digital Comparator 4 Trigger
4
5
read-only
PWM_X_FLTSTAT1_DCMP5
Digital Comparator 5 Trigger
5
6
read-only
PWM_X_FLTSTAT1_DCMP6
Digital Comparator 6 Trigger
6
7
read-only
PWM_X_FLTSTAT1_DCMP7
Digital Comparator 7 Trigger
7
8
read-only
_0_GENA
PWM0 Generator A Control
0x60
-1
read-write
n
0x0
0x0
PWM_X_GENA_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTZERO
Action for Counter=0
0
2
PWM_X_GENA_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x1
PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
0x3
_0_GENB
PWM0 Generator B Control
0x64
-1
read-write
n
0x0
0x0
PWM_X_GENB_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTZERO
Action for Counter=0
0
2
PWM_X_GENB_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x1
PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
0x3
_0_INTEN
PWM0 Interrupt and Trigger Enable
0x44
-1
read-write
n
0x0
0x0
PWM_X_INTEN_INTCMPAD
Interrupt for Counter=PWMnCMPA Down
3
4
PWM_X_INTEN_INTCMPAU
Interrupt for Counter=PWMnCMPA Up
2
3
PWM_X_INTEN_INTCMPBD
Interrupt for Counter=PWMnCMPB Down
5
6
PWM_X_INTEN_INTCMPBU
Interrupt for Counter=PWMnCMPB Up
4
5
PWM_X_INTEN_INTCNTLOAD
Interrupt for Counter=PWMnLOAD
1
2
PWM_X_INTEN_INTCNTZERO
Interrupt for Counter=0
0
1
PWM_X_INTEN_TRCMPAD
Trigger for Counter=PWMnCMPA Down
11
12
PWM_X_INTEN_TRCMPAU
Trigger for Counter=PWMnCMPA Up
10
11
PWM_X_INTEN_TRCMPBD
Trigger for Counter=PWMnCMPB Down
13
14
PWM_X_INTEN_TRCMPBU
Trigger for Counter=PWMnCMPB Up
12
13
PWM_X_INTEN_TRCNTLOAD
Trigger for Counter=PWMnLOAD
9
10
PWM_X_INTEN_TRCNTZERO
Trigger for Counter=0
8
9
_0_ISC
PWM0 Interrupt Status and Clear
0x4C
-1
read-write
n
0x0
0x0
PWM_X_ISC_INTCMPAD
Comparator A Down Interrupt
3
4
PWM_X_ISC_INTCMPAU
Comparator A Up Interrupt
2
3
PWM_X_ISC_INTCMPBD
Comparator B Down Interrupt
5
6
PWM_X_ISC_INTCMPBU
Comparator B Up Interrupt
4
5
PWM_X_ISC_INTCNTLOAD
Counter=Load Interrupt
1
2
PWM_X_ISC_INTCNTZERO
Counter=0 Interrupt
0
1
_0_LOAD
PWM0 Load
0x50
-1
read-write
n
0x0
0x0
PWM_X_LOAD
Counter Load Value
0
16
_0_MINFLTPER
PWM0 Minimum Fault Period
0x7C
-1
read-write
n
0x0
0x0
PWM_X_MINFLTPER
Minimum Fault Period
0
16
_0_RIS
PWM0 Raw Interrupt Status
0x48
-1
read-write
n
0x0
0x0
PWM_X_RIS_INTCMPAD
Comparator A Down Interrupt Status
3
4
PWM_X_RIS_INTCMPAU
Comparator A Up Interrupt Status
2
3
PWM_X_RIS_INTCMPBD
Comparator B Down Interrupt Status
5
6
PWM_X_RIS_INTCMPBU
Comparator B Up Interrupt Status
4
5
PWM_X_RIS_INTCNTLOAD
Counter=Load Interrupt Status
1
2
PWM_X_RIS_INTCNTZERO
Counter=0 Interrupt Status
0
1
_1_CMPA
PWM1 Compare A
0x98
-1
read-write
n
0x0
0x0
_1_CMPB
PWM1 Compare B
0x9C
-1
read-write
n
0x0
0x0
_1_COUNT
PWM1 Counter
0x94
-1
read-write
n
0x0
0x0
_1_CTL
PWM1 Control
0x80
-1
read-write
n
0x0
0x0
_1_DBCTL
PWM1 Dead-Band Control
0xA8
-1
read-write
n
0x0
0x0
_1_DBFALL
PWM1 Dead-Band Falling-Edge-Delay
0xB0
-1
read-write
n
0x0
0x0
_1_DBRISE
PWM1 Dead-Band Rising-Edge Delay
0xAC
-1
read-write
n
0x0
0x0
_1_FLTSEN
PWM1 Fault Pin Logic Sense
0x880
-1
read-write
n
0x0
0x0
_1_FLTSRC0
PWM1 Fault Source 0
0xB4
-1
read-write
n
0x0
0x0
_1_FLTSRC1
PWM1 Fault Source 1
0xB8
-1
read-write
n
0x0
0x0
_1_FLTSTAT0
PWM1 Fault Status 0
0x884
-1
read-only
n
0x0
0x0
_1_FLTSTAT1
PWM1 Fault Status 1
0x888
-1
read-only
n
0x0
0x0
_1_GENA
PWM1 Generator A Control
0xA0
-1
read-write
n
0x0
0x0
_1_GENB
PWM1 Generator B Control
0xA4
-1
read-write
n
0x0
0x0
_1_INTEN
PWM1 Interrupt and Trigger Enable
0x84
-1
read-write
n
0x0
0x0
_1_ISC
PWM1 Interrupt Status and Clear
0x8C
-1
read-write
n
0x0
0x0
_1_LOAD
PWM1 Load
0x90
-1
read-write
n
0x0
0x0
_1_MINFLTPER
PWM1 Minimum Fault Period
0xBC
-1
read-write
n
0x0
0x0
_1_RIS
PWM1 Raw Interrupt Status
0x88
-1
read-write
n
0x0
0x0
_2_CMPA
PWM2 Compare A
0xD8
-1
read-write
n
0x0
0x0
_2_CMPB
PWM2 Compare B
0xDC
-1
read-write
n
0x0
0x0
_2_COUNT
PWM2 Counter
0xD4
-1
read-write
n
0x0
0x0
_2_CTL
PWM2 Control
0xC0
-1
read-write
n
0x0
0x0
_2_DBCTL
PWM2 Dead-Band Control
0xE8
-1
read-write
n
0x0
0x0
_2_DBFALL
PWM2 Dead-Band Falling-Edge-Delay
0xF0
-1
read-write
n
0x0
0x0
_2_DBRISE
PWM2 Dead-Band Rising-Edge Delay
0xEC
-1
read-write
n
0x0
0x0
_2_FLTSEN
PWM2 Fault Pin Logic Sense
0x900
-1
read-write
n
0x0
0x0
_2_FLTSRC0
PWM2 Fault Source 0
0xF4
-1
read-write
n
0x0
0x0
_2_FLTSRC1
PWM2 Fault Source 1
0xF8
-1
read-write
n
0x0
0x0
_2_FLTSTAT0
PWM2 Fault Status 0
0x904
-1
read-only
n
0x0
0x0
_2_FLTSTAT1
PWM2 Fault Status 1
0x908
-1
read-only
n
0x0
0x0
_2_GENA
PWM2 Generator A Control
0xE0
-1
read-write
n
0x0
0x0
_2_GENB
PWM2 Generator B Control
0xE4
-1
read-write
n
0x0
0x0
_2_INTEN
PWM2 Interrupt and Trigger Enable
0xC4
-1
read-write
n
0x0
0x0
_2_ISC
PWM2 Interrupt Status and Clear
0xCC
-1
read-write
n
0x0
0x0
_2_LOAD
PWM2 Load
0xD0
-1
read-write
n
0x0
0x0
_2_MINFLTPER
PWM2 Minimum Fault Period
0xFC
-1
read-write
n
0x0
0x0
_2_RIS
PWM2 Raw Interrupt Status
0xC8
-1
read-write
n
0x0
0x0
_3_FLTSEN
PWM3 Fault Pin Logic Sense
0x980
-1
read-write
n
0x0
0x0
QEI0
Register map for QEI0 peripheral
QEI
0x0
0x0
0x1000
registers
n
COUNT
QEI Velocity Counter
0x18
-1
read-write
n
0x0
0x0
QEI_COUNT
Velocity Pulse Count
0
32
CTL
QEI Control
0x0
-1
read-write
n
0x0
0x0
QEI_CTL_CAPMODE
Capture Mode
3
4
QEI_CTL_ENABLE
Enable QEI
0
1
QEI_CTL_FILTCNT
Input Filter Prescale Count
16
20
QEI_CTL_FILTEN
Enable Input Filter
13
14
QEI_CTL_INVA
Invert PhA
9
10
QEI_CTL_INVB
Invert PhB
10
11
QEI_CTL_INVI
Invert Index Pulse
11
12
QEI_CTL_RESMODE
Reset Mode
4
5
QEI_CTL_SIGMODE
Signal Mode
2
3
QEI_CTL_STALLEN
Stall QEI
12
13
QEI_CTL_SWAP
Swap Signals
1
2
QEI_CTL_VELDIV
Predivide Velocity
6
9
QEI_CTL_VELDIV_1
QEI clock /1
0x0
QEI_CTL_VELDIV_2
QEI clock /2
0x1
QEI_CTL_VELDIV_4
QEI clock /4
0x2
QEI_CTL_VELDIV_8
QEI clock /8
0x3
QEI_CTL_VELDIV_16
QEI clock /16
0x4
QEI_CTL_VELDIV_32
QEI clock /32
0x5
QEI_CTL_VELDIV_64
QEI clock /64
0x6
QEI_CTL_VELDIV_128
QEI clock /128
0x7
QEI_CTL_VELEN
Capture Velocity
5
6
INTEN
QEI Interrupt Enable
0x20
-1
read-write
n
0x0
0x0
QEI_INTEN_DIR
Direction Change Interrupt Enable
2
3
QEI_INTEN_ERROR
Phase Error Interrupt Enable
3
4
QEI_INTEN_INDEX
Index Pulse Detected Interrupt Enable
0
1
QEI_INTEN_TIMER
Timer Expires Interrupt Enable
1
2
ISC
QEI Interrupt Status and Clear
0x28
-1
read-write
n
0x0
0x0
QEI_ISC_DIR
Direction Change Interrupt
2
3
QEI_ISC_ERROR
Phase Error Interrupt
3
4
QEI_ISC_INDEX
Index Pulse Interrupt
0
1
QEI_ISC_TIMER
Velocity Timer Expired Interrupt
1
2
LOAD
QEI Timer Load
0x10
-1
read-write
n
0x0
0x0
QEI_LOAD
Velocity Timer Load Value
0
32
MAXPOS
QEI Maximum Position
0xC
-1
read-write
n
0x0
0x0
QEI_MAXPOS
Maximum Position Integrator Value
0
32
POS
QEI Position
0x8
-1
read-write
n
0x0
0x0
QEI_POS
Current Position Integrator Value
0
32
QEI0COUNT
QEI Velocity Counter
0x18
read-write
n
0x0
0x0
QEI_COUNT
Velocity Pulse Count
0
32
QEI0CTL
QEI Control
0x0
read-write
n
0x0
0x0
QEI_CTL_CAPMODE
Capture Mode
3
4
QEI_CTL_ENABLE
Enable QEI
0
1
QEI_CTL_FILTCNT
Input Filter Prescale Count
16
20
QEI_CTL_FILTEN
Enable Input Filter
13
14
QEI_CTL_INVA
Invert PhA
9
10
QEI_CTL_INVB
Invert PhB
10
11
QEI_CTL_INVI
Invert Index Pulse
11
12
QEI_CTL_RESMODE
Reset Mode
4
5
QEI_CTL_SIGMODE
Signal Mode
2
3
QEI_CTL_STALLEN
Stall QEI
12
13
QEI_CTL_SWAP
Swap Signals
1
2
QEI_CTL_VELDIV
Predivide Velocity
6
9
QEI_CTL_VELDIV_1
QEI clock /1
0x0
QEI_CTL_VELDIV_2
QEI clock /2
0x1
QEI_CTL_VELDIV_4
QEI clock /4
0x2
QEI_CTL_VELDIV_8
QEI clock /8
0x3
QEI_CTL_VELDIV_16
QEI clock /16
0x4
QEI_CTL_VELDIV_32
QEI clock /32
0x5
QEI_CTL_VELDIV_64
QEI clock /64
0x6
QEI_CTL_VELDIV_128
QEI clock /128
0x7
QEI_CTL_VELEN
Capture Velocity
5
6
QEI0INTEN
QEI Interrupt Enable
0x20
read-write
n
0x0
0x0
QEI_INTEN_DIR
Direction Change Interrupt Enable
2
3
QEI_INTEN_ERROR
Phase Error Interrupt Enable
3
4
QEI_INTEN_INDEX
Index Pulse Detected Interrupt Enable
0
1
QEI_INTEN_TIMER
Timer Expires Interrupt Enable
1
2
QEI0ISC
QEI Interrupt Status and Clear
0x28
read-write
n
0x0
0x0
QEI_ISC_DIR
Direction Change Interrupt
2
3
QEI_ISC_ERROR
Phase Error Interrupt
3
4
QEI_ISC_INDEX
Index Pulse Interrupt
0
1
QEI_ISC_TIMER
Velocity Timer Expired Interrupt
1
2
QEI0LOAD
QEI Timer Load
0x10
read-write
n
0x0
0x0
QEI_LOAD
Velocity Timer Load Value
0
32
QEI0MAXPOS
QEI Maximum Position
0xC
read-write
n
0x0
0x0
QEI_MAXPOS
Maximum Position Integrator Value
0
32
QEI0POS
QEI Position
0x8
read-write
n
0x0
0x0
QEI_POS
Current Position Integrator Value
0
32
QEI0RIS
QEI Raw Interrupt Status
0x24
read-write
n
0x0
0x0
QEI_RIS_DIR
Direction Change Detected
2
3
QEI_RIS_ERROR
Phase Error Detected
3
4
QEI_RIS_INDEX
Index Pulse Asserted
0
1
QEI_RIS_TIMER
Velocity Timer Expired
1
2
QEI0SPEED
QEI Velocity
0x1C
read-write
n
0x0
0x0
QEI_SPEED
Velocity
0
32
QEI0STAT
QEI Status
0x4
read-write
n
0x0
0x0
QEI_STAT_DIRECTION
Direction of Rotation
1
2
QEI_STAT_ERROR
Error Detected
0
1
QEI0TIME
QEI Timer
0x14
read-write
n
0x0
0x0
QEI_TIME
Velocity Timer Current Value
0
32
RIS
QEI Raw Interrupt Status
0x24
-1
read-write
n
0x0
0x0
QEI_RIS_DIR
Direction Change Detected
2
3
QEI_RIS_ERROR
Phase Error Detected
3
4
QEI_RIS_INDEX
Index Pulse Asserted
0
1
QEI_RIS_TIMER
Velocity Timer Expired
1
2
SPEED
QEI Velocity
0x1C
-1
read-write
n
0x0
0x0
QEI_SPEED
Velocity
0
32
STAT
QEI Status
0x4
-1
read-write
n
0x0
0x0
QEI_STAT_DIRECTION
Direction of Rotation
1
2
QEI_STAT_ERROR
Error Detected
0
1
TIME
QEI Timer
0x14
-1
read-write
n
0x0
0x0
QEI_TIME
Velocity Timer Current Value
0
32
QEI1
Register map for QEI0 peripheral
QEI
0x0
0x0
0x1000
registers
n
COUNT
QEI Velocity Counter
0x18
-1
read-write
n
0x0
0x0
QEI_COUNT
Velocity Pulse Count
0
32
CTL
QEI Control
0x0
-1
read-write
n
0x0
0x0
QEI_CTL_CAPMODE
Capture Mode
3
4
QEI_CTL_ENABLE
Enable QEI
0
1
QEI_CTL_FILTCNT
Input Filter Prescale Count
16
20
QEI_CTL_FILTEN
Enable Input Filter
13
14
QEI_CTL_INVA
Invert PhA
9
10
QEI_CTL_INVB
Invert PhB
10
11
QEI_CTL_INVI
Invert Index Pulse
11
12
QEI_CTL_RESMODE
Reset Mode
4
5
QEI_CTL_SIGMODE
Signal Mode
2
3
QEI_CTL_STALLEN
Stall QEI
12
13
QEI_CTL_SWAP
Swap Signals
1
2
QEI_CTL_VELDIV
Predivide Velocity
6
9
QEI_CTL_VELDIV_1
QEI clock /1
0x0
QEI_CTL_VELDIV_2
QEI clock /2
0x1
QEI_CTL_VELDIV_4
QEI clock /4
0x2
QEI_CTL_VELDIV_8
QEI clock /8
0x3
QEI_CTL_VELDIV_16
QEI clock /16
0x4
QEI_CTL_VELDIV_32
QEI clock /32
0x5
QEI_CTL_VELDIV_64
QEI clock /64
0x6
QEI_CTL_VELDIV_128
QEI clock /128
0x7
QEI_CTL_VELEN
Capture Velocity
5
6
INTEN
QEI Interrupt Enable
0x20
-1
read-write
n
0x0
0x0
QEI_INTEN_DIR
Direction Change Interrupt Enable
2
3
QEI_INTEN_ERROR
Phase Error Interrupt Enable
3
4
QEI_INTEN_INDEX
Index Pulse Detected Interrupt Enable
0
1
QEI_INTEN_TIMER
Timer Expires Interrupt Enable
1
2
ISC
QEI Interrupt Status and Clear
0x28
-1
read-write
n
0x0
0x0
QEI_ISC_DIR
Direction Change Interrupt
2
3
QEI_ISC_ERROR
Phase Error Interrupt
3
4
QEI_ISC_INDEX
Index Pulse Interrupt
0
1
QEI_ISC_TIMER
Velocity Timer Expired Interrupt
1
2
LOAD
QEI Timer Load
0x10
-1
read-write
n
0x0
0x0
QEI_LOAD
Velocity Timer Load Value
0
32
MAXPOS
QEI Maximum Position
0xC
-1
read-write
n
0x0
0x0
QEI_MAXPOS
Maximum Position Integrator Value
0
32
POS
QEI Position
0x8
-1
read-write
n
0x0
0x0
QEI_POS
Current Position Integrator Value
0
32
QEI0COUNT
QEI Velocity Counter
0x18
read-write
n
0x0
0x0
QEI_COUNT
Velocity Pulse Count
0
32
QEI0CTL
QEI Control
0x0
read-write
n
0x0
0x0
QEI_CTL_CAPMODE
Capture Mode
3
4
QEI_CTL_ENABLE
Enable QEI
0
1
QEI_CTL_FILTCNT
Input Filter Prescale Count
16
20
QEI_CTL_FILTEN
Enable Input Filter
13
14
QEI_CTL_INVA
Invert PhA
9
10
QEI_CTL_INVB
Invert PhB
10
11
QEI_CTL_INVI
Invert Index Pulse
11
12
QEI_CTL_RESMODE
Reset Mode
4
5
QEI_CTL_SIGMODE
Signal Mode
2
3
QEI_CTL_STALLEN
Stall QEI
12
13
QEI_CTL_SWAP
Swap Signals
1
2
QEI_CTL_VELDIV
Predivide Velocity
6
9
QEI_CTL_VELDIV_1
QEI clock /1
0x0
QEI_CTL_VELDIV_2
QEI clock /2
0x1
QEI_CTL_VELDIV_4
QEI clock /4
0x2
QEI_CTL_VELDIV_8
QEI clock /8
0x3
QEI_CTL_VELDIV_16
QEI clock /16
0x4
QEI_CTL_VELDIV_32
QEI clock /32
0x5
QEI_CTL_VELDIV_64
QEI clock /64
0x6
QEI_CTL_VELDIV_128
QEI clock /128
0x7
QEI_CTL_VELEN
Capture Velocity
5
6
QEI0INTEN
QEI Interrupt Enable
0x20
read-write
n
0x0
0x0
QEI_INTEN_DIR
Direction Change Interrupt Enable
2
3
QEI_INTEN_ERROR
Phase Error Interrupt Enable
3
4
QEI_INTEN_INDEX
Index Pulse Detected Interrupt Enable
0
1
QEI_INTEN_TIMER
Timer Expires Interrupt Enable
1
2
QEI0ISC
QEI Interrupt Status and Clear
0x28
read-write
n
0x0
0x0
QEI_ISC_DIR
Direction Change Interrupt
2
3
QEI_ISC_ERROR
Phase Error Interrupt
3
4
QEI_ISC_INDEX
Index Pulse Interrupt
0
1
QEI_ISC_TIMER
Velocity Timer Expired Interrupt
1
2
QEI0LOAD
QEI Timer Load
0x10
read-write
n
0x0
0x0
QEI_LOAD
Velocity Timer Load Value
0
32
QEI0MAXPOS
QEI Maximum Position
0xC
read-write
n
0x0
0x0
QEI_MAXPOS
Maximum Position Integrator Value
0
32
QEI0POS
QEI Position
0x8
read-write
n
0x0
0x0
QEI_POS
Current Position Integrator Value
0
32
QEI0RIS
QEI Raw Interrupt Status
0x24
read-write
n
0x0
0x0
QEI_RIS_DIR
Direction Change Detected
2
3
QEI_RIS_ERROR
Phase Error Detected
3
4
QEI_RIS_INDEX
Index Pulse Asserted
0
1
QEI_RIS_TIMER
Velocity Timer Expired
1
2
QEI0SPEED
QEI Velocity
0x1C
read-write
n
0x0
0x0
QEI_SPEED
Velocity
0
32
QEI0STAT
QEI Status
0x4
read-write
n
0x0
0x0
QEI_STAT_DIRECTION
Direction of Rotation
1
2
QEI_STAT_ERROR
Error Detected
0
1
QEI0TIME
QEI Timer
0x14
read-write
n
0x0
0x0
QEI_TIME
Velocity Timer Current Value
0
32
RIS
QEI Raw Interrupt Status
0x24
-1
read-write
n
0x0
0x0
QEI_RIS_DIR
Direction Change Detected
2
3
QEI_RIS_ERROR
Phase Error Detected
3
4
QEI_RIS_INDEX
Index Pulse Asserted
0
1
QEI_RIS_TIMER
Velocity Timer Expired
1
2
SPEED
QEI Velocity
0x1C
-1
read-write
n
0x0
0x0
QEI_SPEED
Velocity
0
32
STAT
QEI Status
0x4
-1
read-write
n
0x0
0x0
QEI_STAT_DIRECTION
Direction of Rotation
1
2
QEI_STAT_ERROR
Error Detected
0
1
TIME
QEI Timer
0x14
-1
read-write
n
0x0
0x0
QEI_TIME
Velocity Timer Current Value
0
32
SSI0
Register map for SSI0 peripheral
SSI
0x0
0x0
0x1000
registers
n
CPSR
SSI Clock Prescale
0x10
-1
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
CR0
SSI Control 0
0x0
-1
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
CR1
SSI Control 1
0x4
-1
read-write
n
0x0
0x0
SSI_CR1_EOT
End of Transmission
4
5
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
DMACTL
SSI DMA Control
0x24
-1
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
SSI Data
0x8
-1
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
ICR
SSI Interrupt Clear
0x20
-1
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
IM
SSI Interrupt Mask
0x14
-1
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
MIS
SSI Masked Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
RIS
SSI Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SR
SSI Status
0xC
-1
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SSI0CPSR
SSI Clock Prescale
0x10
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
SSI0CR0
SSI Control 0
0x0
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
SSI0CR1
SSI Control 1
0x4
read-write
n
0x0
0x0
SSI_CR1_EOT
End of Transmission
4
5
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
SSI0DMACTL
SSI DMA Control
0x24
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
SSI0DR
SSI Data
0x8
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
SSI0ICR
SSI Interrupt Clear
0x20
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
SSI0IM
SSI Interrupt Mask
0x14
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
SSI0MIS
SSI Masked Interrupt Status
0x1C
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
SSI0RIS
SSI Raw Interrupt Status
0x18
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SSI0SR
SSI Status
0xC
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SSI1
Register map for SSI0 peripheral
SSI
0x0
0x0
0x1000
registers
n
CPSR
SSI Clock Prescale
0x10
-1
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
CR0
SSI Control 0
0x0
-1
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
CR1
SSI Control 1
0x4
-1
read-write
n
0x0
0x0
SSI_CR1_EOT
End of Transmission
4
5
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
DMACTL
SSI DMA Control
0x24
-1
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
SSI Data
0x8
-1
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
ICR
SSI Interrupt Clear
0x20
-1
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
IM
SSI Interrupt Mask
0x14
-1
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
MIS
SSI Masked Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
RIS
SSI Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SR
SSI Status
0xC
-1
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SSI0CPSR
SSI Clock Prescale
0x10
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
SSI0CR0
SSI Control 0
0x0
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
SSI0CR1
SSI Control 1
0x4
read-write
n
0x0
0x0
SSI_CR1_EOT
End of Transmission
4
5
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
SSI0DMACTL
SSI DMA Control
0x24
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
SSI0DR
SSI Data
0x8
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
SSI0ICR
SSI Interrupt Clear
0x20
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
SSI0IM
SSI Interrupt Mask
0x14
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
SSI0MIS
SSI Masked Interrupt Status
0x1C
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
SSI0RIS
SSI Raw Interrupt Status
0x18
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SSI0SR
SSI Status
0xC
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SYSCTL
Register map for SYSCTL peripheral
SYSCTL
0x0
0x0
0x1000
registers
n
DC0
Device Capabilities 0
0x8
-1
read-write
n
0x0
0x0
SYSCTL_DC0_FLASHSZ
Flash Size
0
16
SYSCTL_DC0_FLASHSZ_256K
256 KB of Flash
0x7f
SYSCTL_DC0_SRAMSZ
SRAM Size
16
32
SYSCTL_DC0_SRAMSZ_64KB
64 KB of SRAM
0xff
DC1
Device Capabilities 1
0x10
-1
read-write
n
0x0
0x0
SYSCTL_DC1_ADC0
ADC Module 0 Present
16
17
SYSCTL_DC1_ADC0SPD
Max ADC0 Speed
8
10
SYSCTL_DC1_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_DC1_ADC1
ADC Module 1 Present
17
18
SYSCTL_DC1_ADC1SPD
Max ADC1 Speed
10
12
SYSCTL_DC1_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_DC1_CAN0
CAN Module 0 Present
24
25
SYSCTL_DC1_CAN1
CAN Module 1 Present
25
26
SYSCTL_DC1_HIB
Hibernation Module Present
6
7
SYSCTL_DC1_JTAG
JTAG Present
0
1
SYSCTL_DC1_MINSYSDIV
System Clock Divider
12
16
SYSCTL_DC1_MINSYSDIV_100
Divide VCO (400MHZ) by 5 minimum
0x1
SYSCTL_DC1_MINSYSDIV_66
Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum
0x2
SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x3
SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
0x7
SYSCTL_DC1_MINSYSDIV_20
Specifies a 20-MHz clock with a PLL divider of 10
0x9
SYSCTL_DC1_MPU
MPU Present
7
8
SYSCTL_DC1_PLL
PLL Present
4
5
SYSCTL_DC1_SWD
SWD Present
1
2
SYSCTL_DC1_SWO
SWO Trace Port Present
2
3
SYSCTL_DC1_TEMP
Temp Sensor Present
5
6
SYSCTL_DC1_WDT0
Watchdog Timer 0 Present
3
4
SYSCTL_DC1_WDT1
Watchdog Timer1 Present
28
29
DC2
Device Capabilities 2
0x14
-1
read-write
n
0x0
0x0
SYSCTL_DC2_COMP0
Analog Comparator 0 Present
24
25
SYSCTL_DC2_COMP1
Analog Comparator 1 Present
25
26
SYSCTL_DC2_I2C0
I2C Module 0 Present
12
13
SYSCTL_DC2_I2C1
I2C Module 1 Present
14
15
SYSCTL_DC2_I2S0
I2S Module 0 Present
28
29
SYSCTL_DC2_QEI0
QEI Module 0 Present
8
9
SYSCTL_DC2_QEI1
QEI Module 1 Present
9
10
SYSCTL_DC2_SSI0
SSI Module 0 Present
4
5
SYSCTL_DC2_SSI1
SSI Module 1 Present
5
6
SYSCTL_DC2_TIMER0
Timer Module 0 Present
16
17
SYSCTL_DC2_TIMER1
Timer Module 1 Present
17
18
SYSCTL_DC2_TIMER2
Timer Module 2 Present
18
19
SYSCTL_DC2_TIMER3
Timer Module 3 Present
19
20
SYSCTL_DC2_UART0
UART Module 0 Present
0
1
SYSCTL_DC2_UART1
UART Module 1 Present
1
2
SYSCTL_DC2_UART2
UART Module 2 Present
2
3
DC3
Device Capabilities 3
0x18
-1
read-write
n
0x0
0x0
SYSCTL_DC3_32KHZ
32KHz Input Clock Available
31
32
SYSCTL_DC3_ADC0AIN0
ADC Module 0 AIN0 Pin Present
16
17
SYSCTL_DC3_ADC0AIN1
ADC Module 0 AIN1 Pin Present
17
18
SYSCTL_DC3_ADC0AIN2
ADC Module 0 AIN2 Pin Present
18
19
SYSCTL_DC3_ADC0AIN3
ADC Module 0 AIN3 Pin Present
19
20
SYSCTL_DC3_ADC0AIN4
ADC Module 0 AIN4 Pin Present
20
21
SYSCTL_DC3_ADC0AIN5
ADC Module 0 AIN5 Pin Present
21
22
SYSCTL_DC3_ADC0AIN6
ADC Module 0 AIN6 Pin Present
22
23
SYSCTL_DC3_ADC0AIN7
ADC Module 0 AIN7 Pin Present
23
24
SYSCTL_DC3_C0MINUS
C0- Pin Present
6
7
SYSCTL_DC3_C0O
C0o Pin Present
8
9
SYSCTL_DC3_C0PLUS
C0+ Pin Present
7
8
SYSCTL_DC3_C1MINUS
C1- Pin Present
9
10
SYSCTL_DC3_C1O
C1o Pin Present
11
12
SYSCTL_DC3_C1PLUS
C1+ Pin Present
10
11
SYSCTL_DC3_CCP0
CCP0 Pin Present
24
25
SYSCTL_DC3_CCP1
CCP1 Pin Present
25
26
SYSCTL_DC3_CCP2
CCP2 Pin Present
26
27
SYSCTL_DC3_CCP3
CCP3 Pin Present
27
28
SYSCTL_DC3_CCP4
CCP4 Pin Present
28
29
SYSCTL_DC3_CCP5
CCP5 Pin Present
29
30
SYSCTL_DC3_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC3_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC3_PWM2
PWM2 Pin Present
2
3
SYSCTL_DC3_PWM3
PWM3 Pin Present
3
4
SYSCTL_DC3_PWM4
PWM4 Pin Present
4
5
SYSCTL_DC3_PWM5
PWM5 Pin Present
5
6
SYSCTL_DC3_PWMFAULT
PWM Fault Pin Present
15
16
DC4
Device Capabilities 4
0x1C
-1
read-write
n
0x0
0x0
SYSCTL_DC4_CCP6
CCP6 Pin Present
14
15
SYSCTL_DC4_CCP7
CCP7 Pin Present
15
16
SYSCTL_DC4_E1588
1588 Capable
24
25
SYSCTL_DC4_EMAC0
Ethernet MAC Layer 0 Present
28
29
SYSCTL_DC4_EPHY0
Ethernet PHY Layer 0 Present
30
31
SYSCTL_DC4_GPIOA
GPIO Port A Present
0
1
SYSCTL_DC4_GPIOB
GPIO Port B Present
1
2
SYSCTL_DC4_GPIOC
GPIO Port C Present
2
3
SYSCTL_DC4_GPIOD
GPIO Port D Present
3
4
SYSCTL_DC4_GPIOE
GPIO Port E Present
4
5
SYSCTL_DC4_GPIOF
GPIO Port F Present
5
6
SYSCTL_DC4_GPIOG
GPIO Port G Present
6
7
SYSCTL_DC4_GPIOH
GPIO Port H Present
7
8
SYSCTL_DC4_GPIOJ
GPIO Port J Present
8
9
SYSCTL_DC4_PICAL
PIOSC Calibrate
18
19
SYSCTL_DC4_ROM
Internal Code ROM Present
12
13
SYSCTL_DC4_UDMA
Micro-DMA Module Present
13
14
DC5
Device Capabilities 5
0x20
-1
read-write
n
0x0
0x0
SYSCTL_DC5_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC5_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC5_PWM2
PWM2 Pin Present
2
3
SYSCTL_DC5_PWM3
PWM3 Pin Present
3
4
SYSCTL_DC5_PWM4
PWM4 Pin Present
4
5
SYSCTL_DC5_PWM5
PWM5 Pin Present
5
6
SYSCTL_DC5_PWMEFLT
PWM Extended Fault Active
21
22
SYSCTL_DC5_PWMESYNC
PWM Extended SYNC Active
20
21
SYSCTL_DC5_PWMFAULT0
PWM Fault 0 Pin Present
24
25
SYSCTL_DC5_PWMFAULT1
PWM Fault 1 Pin Present
25
26
SYSCTL_DC5_PWMFAULT2
PWM Fault 2 Pin Present
26
27
SYSCTL_DC5_PWMFAULT3
PWM Fault 3 Pin Present
27
28
DC6
Device Capabilities 6
0x24
-1
read-write
n
0x0
0x0
SYSCTL_DC6_USB0
USB Module 0 Present
0
2
SYSCTL_DC6_USB0_OTG
USB0 is OTG
0x3
SYSCTL_DC6_USB0PHY
USB Module 0 PHY Present
4
5
DC7
Device Capabilities 7
0x28
-1
read-write
n
0x0
0x0
SYSCTL_DC7_DMACH0
USB_EP1_RX / UART2_RX
0
1
SYSCTL_DC7_DMACH1
USB_EP1_TX / UART2_TX
1
2
SYSCTL_DC7_DMACH10
SSI0_RX / SSI1_RX
10
11
SYSCTL_DC7_DMACH11
SSI0_TX / SSI1_TX
11
12
SYSCTL_DC7_DMACH12
CAN0_RX / UART2_RX
12
13
SYSCTL_DC7_DMACH13
CAN0_TX / UART2_TX
13
14
SYSCTL_DC7_DMACH14
ADC0_SS0 / Timer2A
14
15
SYSCTL_DC7_DMACH15
ADC0_SS1 / Timer2B
15
16
SYSCTL_DC7_DMACH16
ADC0_SS2
16
17
SYSCTL_DC7_DMACH17
ADC0_SS3
17
18
SYSCTL_DC7_DMACH18
Timer0A / Timer1A
18
19
SYSCTL_DC7_DMACH19
Timer0B / Timer1B
19
20
SYSCTL_DC7_DMACH2
USB_EP2_RX / Timer3A
2
3
SYSCTL_DC7_DMACH20
Timer1A / EPI0_NBRFIFO
20
21
SYSCTL_DC7_DMACH21
Timer1B / EPI0_WFIFO
21
22
SYSCTL_DC7_DMACH22
UART1_RX / CAN2_RX
22
23
SYSCTL_DC7_DMACH23
UART1_TX / CAN2_TX
23
24
SYSCTL_DC7_DMACH24
SSI1_RX / ADC1_SS0
24
25
SYSCTL_DC7_DMACH25
SSI1_TX / ADC1_SS1
25
26
SYSCTL_DC7_DMACH26
CAN1_RX / ADC1_SS2
26
27
SYSCTL_DC7_DMACH27
CAN1_TX / ADC1_SS3
27
28
SYSCTL_DC7_DMACH28
I2S0_RX / CAN1_RX
28
29
SYSCTL_DC7_DMACH29
I2S0_TX / CAN1_TX
29
30
SYSCTL_DC7_DMACH3
USB_EP2_TX / Timer3B
3
4
SYSCTL_DC7_DMACH30
SW
30
31
SYSCTL_DC7_DMACH4
USB_EP3_RX / Timer2A
4
5
SYSCTL_DC7_DMACH5
USB_EP3_TX / Timer2B
5
6
SYSCTL_DC7_DMACH6
ETH_RX / Timer2A
6
7
SYSCTL_DC7_DMACH7
ETH_TX / Timer2B
7
8
SYSCTL_DC7_DMACH8
UART0_RX / UART1_RX
8
9
SYSCTL_DC7_DMACH9
UART0_TX / UART1_TX
9
10
DC8
Device Capabilities 8 ADC Channels
0x2C
-1
read-write
n
0x0
0x0
SYSCTL_DC8_ADC0AIN0
ADC Module 0 AIN0 Pin Present
0
1
SYSCTL_DC8_ADC0AIN1
ADC Module 0 AIN1 Pin Present
1
2
SYSCTL_DC8_ADC0AIN10
ADC Module 0 AIN10 Pin Present
10
11
SYSCTL_DC8_ADC0AIN11
ADC Module 0 AIN11 Pin Present
11
12
SYSCTL_DC8_ADC0AIN12
ADC Module 0 AIN12 Pin Present
12
13
SYSCTL_DC8_ADC0AIN13
ADC Module 0 AIN13 Pin Present
13
14
SYSCTL_DC8_ADC0AIN14
ADC Module 0 AIN14 Pin Present
14
15
SYSCTL_DC8_ADC0AIN15
ADC Module 0 AIN15 Pin Present
15
16
SYSCTL_DC8_ADC0AIN2
ADC Module 0 AIN2 Pin Present
2
3
SYSCTL_DC8_ADC0AIN3
ADC Module 0 AIN3 Pin Present
3
4
SYSCTL_DC8_ADC0AIN4
ADC Module 0 AIN4 Pin Present
4
5
SYSCTL_DC8_ADC0AIN5
ADC Module 0 AIN5 Pin Present
5
6
SYSCTL_DC8_ADC0AIN6
ADC Module 0 AIN6 Pin Present
6
7
SYSCTL_DC8_ADC0AIN7
ADC Module 0 AIN7 Pin Present
7
8
SYSCTL_DC8_ADC0AIN8
ADC Module 0 AIN8 Pin Present
8
9
SYSCTL_DC8_ADC0AIN9
ADC Module 0 AIN9 Pin Present
9
10
SYSCTL_DC8_ADC1AIN0
ADC Module 1 AIN0 Pin Present
16
17
SYSCTL_DC8_ADC1AIN1
ADC Module 1 AIN1 Pin Present
17
18
SYSCTL_DC8_ADC1AIN10
ADC Module 1 AIN10 Pin Present
26
27
SYSCTL_DC8_ADC1AIN11
ADC Module 1 AIN11 Pin Present
27
28
SYSCTL_DC8_ADC1AIN12
ADC Module 1 AIN12 Pin Present
28
29
SYSCTL_DC8_ADC1AIN13
ADC Module 1 AIN13 Pin Present
29
30
SYSCTL_DC8_ADC1AIN14
ADC Module 1 AIN14 Pin Present
30
31
SYSCTL_DC8_ADC1AIN15
ADC Module 1 AIN15 Pin Present
31
32
SYSCTL_DC8_ADC1AIN2
ADC Module 1 AIN2 Pin Present
18
19
SYSCTL_DC8_ADC1AIN3
ADC Module 1 AIN3 Pin Present
19
20
SYSCTL_DC8_ADC1AIN4
ADC Module 1 AIN4 Pin Present
20
21
SYSCTL_DC8_ADC1AIN5
ADC Module 1 AIN5 Pin Present
21
22
SYSCTL_DC8_ADC1AIN6
ADC Module 1 AIN6 Pin Present
22
23
SYSCTL_DC8_ADC1AIN7
ADC Module 1 AIN7 Pin Present
23
24
SYSCTL_DC8_ADC1AIN8
ADC Module 1 AIN8 Pin Present
24
25
SYSCTL_DC8_ADC1AIN9
ADC Module 1 AIN9 Pin Present
25
26
DC9
Device Capabilities 9 ADC Digital Comparators
0x190
-1
read-write
n
0x0
0x0
SYSCTL_DC9_ADC0DC0
ADC0 DC0 Present
0
1
SYSCTL_DC9_ADC0DC1
ADC0 DC1 Present
1
2
SYSCTL_DC9_ADC0DC2
ADC0 DC2 Present
2
3
SYSCTL_DC9_ADC0DC3
ADC0 DC3 Present
3
4
SYSCTL_DC9_ADC0DC4
ADC0 DC4 Present
4
5
SYSCTL_DC9_ADC0DC5
ADC0 DC5 Present
5
6
SYSCTL_DC9_ADC0DC6
ADC0 DC6 Present
6
7
SYSCTL_DC9_ADC0DC7
ADC0 DC7 Present
7
8
SYSCTL_DC9_ADC1DC0
ADC1 DC0 Present
16
17
SYSCTL_DC9_ADC1DC1
ADC1 DC1 Present
17
18
SYSCTL_DC9_ADC1DC2
ADC1 DC2 Present
18
19
SYSCTL_DC9_ADC1DC3
ADC1 DC3 Present
19
20
SYSCTL_DC9_ADC1DC4
ADC1 DC4 Present
20
21
SYSCTL_DC9_ADC1DC5
ADC1 DC5 Present
21
22
SYSCTL_DC9_ADC1DC6
ADC1 DC6 Present
22
23
SYSCTL_DC9_ADC1DC7
ADC1 DC7 Present
23
24
DCGC0
Deep Sleep Mode Clock Gating Control Register 0
0x120
-1
read-write
n
0x0
0x0
SYSCTL_DCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_DCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_DCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_DCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_DCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_DCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_DCGC0_WDT1
WDT1 Clock Gating Control
28
29
DCGC1
Deep-Sleep Mode Clock Gating Control Register 1
0x124
-1
read-write
n
0x0
0x0
SYSCTL_DCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_DCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_DCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_DCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_DCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_DCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_DCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_DCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_DCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_DCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_DCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_DCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_DCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_DCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_DCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_DCGC1_UART2
UART2 Clock Gating Control
2
3
DCGC2
Deep Sleep Mode Clock Gating Control Register 2
0x128
-1
read-write
n
0x0
0x0
SYSCTL_DCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_DCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_DCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_DCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_DCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_DCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_DCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_DCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_DCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_DCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_DCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_DCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_DCGC2_USB0
USB0 Clock Gating Control
16
17
DID0
Device Identification 0
0x0
-1
read-write
n
0x0
0x0
SYSCTL_DID0_CLASS
Device Class
16
24
SYSCTL_DID0_CLASS_TEMPEST
Stellaris(R) Tempest-class microcontrollers
0x4
SYSCTL_DID0_MAJ
Major Revision
8
16
SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x0
SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x1
SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
0x2
SYSCTL_DID0_MIN
Minor Revision
0
8
SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x0
SYSCTL_DID0_MIN_1
First metal layer change
0x1
SYSCTL_DID0_MIN_2
Second metal layer change
0x2
SYSCTL_DID0_VER
DID0 Version
28
31
SYSCTL_DID0_VER_1
Second version of the DID0 register format
0x1
DID1
Device Identification 1
0x4
-1
read-write
n
0x0
0x0
SYSCTL_DID1_FAM
Family
24
28
SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
0x0
SYSCTL_DID1_PINCNT
Package Pin Count
13
16
SYSCTL_DID1_PINCNT_100
100-pin package
0x2
SYSCTL_DID1_PKG
Package Type
3
5
SYSCTL_DID1_PKG_SOIC
SOIC package
0x0
SYSCTL_DID1_PKG_QFP
LQFP package
0x1
SYSCTL_DID1_PKG_BGA
BGA package
0x2
SYSCTL_DID1_PRTNO
Part Number
16
24
SYSCTL_DID1_PRTNO_9997
LM3S9997
0x20
SYSCTL_DID1_QUAL
Qualification Status
0
2
SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x0
SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x1
SYSCTL_DID1_QUAL_FQ
Fully Qualified
0x2
SYSCTL_DID1_ROHS
RoHS-Compliance
2
3
SYSCTL_DID1_TEMP
Temperature Range
5
8
SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x0
SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x1
SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
0x2
SYSCTL_DID1_VER
DID1 Version
28
32
SYSCTL_DID1_VER_1
Second version of the DID1 register format
0x1
DSLPCLKCFG
Deep Sleep Clock Configuration
0x144
-1
read-write
n
0x0
0x0
SYSCTL_DSLPCLKCFG_D
Divider Field Override
23
29
SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x0
SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x1
SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x10
SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x11
SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x12
SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x13
SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x14
SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x15
SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x16
SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x17
SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x18
SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x19
SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1a
SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1b
SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1c
SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1d
SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1e
SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x1f
SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x2
SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x20
SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x21
SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x22
SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x23
SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x24
SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x25
SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x26
SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x27
SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x28
SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x29
SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2a
SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2b
SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2c
SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2d
SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2e
SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x2f
SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x3
SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x30
SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x31
SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x32
SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x33
SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x34
SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x35
SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x36
SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x37
SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x38
SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x39
SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3a
SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3b
SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3c
SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3d
SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3e
SYSCTL_DSLPCLKCFG_D_64
System clock /64
0x3f
SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x4
SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x5
SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x6
SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x7
SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x8
SYSCTL_DSLPCLKCFG_D_10
System clock /10
0x9
SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xa
SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xb
SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xc
SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xd
SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xe
SYSCTL_DSLPCLKCFG_D_16
System clock /16
0xf
SYSCTL_DSLPCLKCFG_O
Clock Source
4
7
SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x0
SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x1
SYSCTL_DSLPCLKCFG_O_30
30 kHz
0x3
SYSCTL_DSLPCLKCFG_O_32
32.768 kHz
0x7
GPIOHBCTL
GPIO High-Performance Bus Control
0x6C
-1
read-write
n
0x0
0x0
SYSCTL_GPIOHBCTL_PORTA
Port A Advanced High-Performance Bus
0
1
SYSCTL_GPIOHBCTL_PORTB
Port B Advanced High-Performance Bus
1
2
SYSCTL_GPIOHBCTL_PORTC
Port C Advanced High-Performance Bus
2
3
SYSCTL_GPIOHBCTL_PORTD
Port D Advanced High-Performance Bus
3
4
SYSCTL_GPIOHBCTL_PORTE
Port E Advanced High-Performance Bus
4
5
SYSCTL_GPIOHBCTL_PORTF
Port F Advanced High-Performance Bus
5
6
SYSCTL_GPIOHBCTL_PORTG
Port G Advanced High-Performance Bus
6
7
SYSCTL_GPIOHBCTL_PORTH
Port H Advanced High-Performance Bus
7
8
SYSCTL_GPIOHBCTL_PORTJ
Port J Advanced High-Performance Bus
8
9
I2SMCLKCFG
I2S MCLK Configuration
0x170
-1
read-write
n
0x0
0x0
SYSCTL_I2SMCLKCFG_RXEN
RX Clock Enable
31
32
SYSCTL_I2SMCLKCFG_RXF
RX Clock Fractional Input
16
20
SYSCTL_I2SMCLKCFG_RXI
RX Clock Integer Input
20
30
SYSCTL_I2SMCLKCFG_TXEN
TX Clock Enable
15
16
SYSCTL_I2SMCLKCFG_TXF
TX Clock Fractional Input
0
4
SYSCTL_I2SMCLKCFG_TXI
TX Clock Integer Input
4
14
IMC
Interrupt Mask Control
0x54
-1
read-write
n
0x0
0x0
SYSCTL_IMC_BORIM
Brown-Out Reset Interrupt Mask
1
2
SYSCTL_IMC_MOSCPUPIM
MOSC Power Up Interrupt Mask
8
9
SYSCTL_IMC_PLLLIM
PLL Lock Interrupt Mask
6
7
SYSCTL_IMC_USBPLLLIM
USB PLL Lock Interrupt Mask
7
8
MISC
Masked Interrupt Status and Clear
0x58
-1
read-write
n
0x0
0x0
SYSCTL_MISC_BORMIS
BOR Masked Interrupt Status
1
2
SYSCTL_MISC_MOSCPUPMIS
MOSC Power Up Masked Interrupt Status
8
9
SYSCTL_MISC_PLLLMIS
PLL Lock Masked Interrupt Status
6
7
SYSCTL_MISC_USBPLLLMIS
USB PLL Lock Masked Interrupt Status
7
8
MOSCCTL
Main Oscillator Control
0x7C
-1
read-write
n
0x0
0x0
SYSCTL_MOSCCTL_CVAL
Clock Validation for MOSC
0
1
NVMSTAT
Non-Volatile Memory Information
0x1A0
-1
read-write
n
0x0
0x0
SYSCTL_NVMSTAT_FWB
32 Word Flash Write Buffer Active
0
1
PBORCTL
Brown-Out Reset Control
0x30
-1
read-write
n
0x0
0x0
SYSCTL_PBORCTL_BORIOR
BOR Interrupt or Reset
1
2
PIOSCCAL
Precision Internal Oscillator Calibration
0x150
-1
read-write
n
0x0
0x0
SYSCTL_PIOSCCAL_CAL
Start Calibration
9
10
SYSCTL_PIOSCCAL_UPDATE
Update Trim
8
9
SYSCTL_PIOSCCAL_UT
User Trim Value
0
7
SYSCTL_PIOSCCAL_UTEN
Use User Trim Value
31
32
PIOSCSTAT
Precision Internal Oscillator Statistics
0x154
-1
read-write
n
0x0
0x0
SYSCTL_PIOSCSTAT_CR
Calibration Result
8
10
SYSCTL_PIOSCSTAT_CRNONE
Calibration has not been attempted
0x0
SYSCTL_PIOSCSTAT_CRPASS
The last calibration operation completed to meet 1% accuracy
0x1
SYSCTL_PIOSCSTAT_CRFAIL
The last calibration operation failed to meet 1% accuracy
0x2
SYSCTL_PIOSCSTAT_CT
Calibration Trim Value
0
7
SYSCTL_PIOSCSTAT_DT
Default Trim Value
16
23
PLLCFG
XTAL to PLL Translation
0x64
-1
read-write
n
0x0
0x0
SYSCTL_PLLCFG_F
PLL F Value
5
14
SYSCTL_PLLCFG_R
PLL R Value
0
5
RCC
Run-Mode Clock Configuration
0x60
-1
read-write
n
0x0
0x0
SYSCTL_RCC_ACG
Auto Clock Gating
27
28
SYSCTL_RCC_BYPASS
PLL Bypass
11
12
SYSCTL_RCC_IOSCDIS
Internal Oscillator Disable
1
2
SYSCTL_RCC_MOSCDIS
Main Oscillator Disable
0
1
SYSCTL_RCC_OSCSRC
Oscillator Source
4
6
SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x0
SYSCTL_RCC_OSCSRC_INT
IOSC
0x1
SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x2
SYSCTL_RCC_OSCSRC_30
30 kHz
0x3
SYSCTL_RCC_PWMDIV
PWM Unit Clock Divisor
17
20
SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x0
SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x1
SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x2
SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x3
SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x4
SYSCTL_RCC_PWMDIV_64
PWM clock /64
0x5
SYSCTL_RCC_PWRDN
PLL Power Down
13
14
SYSCTL_RCC_SYSDIV
System Clock Divisor
23
27
SYSCTL_RCC_USEPWMDIV
Enable PWM Clock Divisor
20
21
SYSCTL_RCC_USESYSDIV
Enable System Clock Divider
22
23
SYSCTL_RCC_XTAL
Crystal Value
6
11
SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x0
SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x1
SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x10
SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x11
SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x12
SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x13
SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x14
SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x15
SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
0x16
SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x2
SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x3
SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x4
SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x5
SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x6
SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x7
SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x8
SYSCTL_RCC_XTAL_5MHZ
5 MHz
0x9
SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xa
SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xb
SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xc
SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xd
SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xe
SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0xf
RCC2
Run-Mode Clock Configuration 2
0x70
-1
read-write
n
0x0
0x0
SYSCTL_RCC2_BYPASS2
PLL Bypass 2
11
12
SYSCTL_RCC2_DIV400
Divide PLL as 400 MHz vs. 200 MHz
30
31
SYSCTL_RCC2_OSCSRC2
Oscillator Source 2
4
7
SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x0
SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x1
SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x2
SYSCTL_RCC2_OSCSRC2_30
30 kHz
0x3
SYSCTL_RCC2_OSCSRC2_419
4.194304 MHz
0x6
SYSCTL_RCC2_OSCSRC2_32
32.768 kHz
0x7
SYSCTL_RCC2_PWRDN2
Power-Down PLL 2
13
14
SYSCTL_RCC2_SYSDIV2
System Clock Divisor 2
23
29
SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x1
SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x10
SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x11
SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x12
SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x13
SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x14
SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x15
SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x16
SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x17
SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x18
SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x19
SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1a
SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1b
SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1c
SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1d
SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1e
SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x1f
SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x2
SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x20
SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x21
SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x22
SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x23
SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x24
SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x25
SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x26
SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x27
SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x28
SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x29
SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2a
SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2b
SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2c
SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2d
SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2e
SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x2f
SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x3
SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x30
SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x31
SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x32
SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x33
SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x34
SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x35
SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x36
SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x37
SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x38
SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x39
SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3a
SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3b
SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3c
SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3d
SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3e
SYSCTL_RCC2_SYSDIV2_64
System clock /64
0x3f
SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x4
SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x5
SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x6
SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x7
SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x8
SYSCTL_RCC2_SYSDIV2_10
System clock /10
0x9
SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xa
SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xb
SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xc
SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xd
SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xe
SYSCTL_RCC2_SYSDIV2_16
System clock /16
0xf
SYSCTL_RCC2_SYSDIV2LSB
Additional LSB for SYSDIV2
22
23
SYSCTL_RCC2_USBPWRDN
Power-Down USB PLL
14
15
SYSCTL_RCC2_USERCC2
Use RCC2
31
32
RCGC0
Run Mode Clock Gating Control Register 0
0x100
-1
read-write
n
0x0
0x0
SYSCTL_RCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_RCGC0_ADC0SPD
ADC0 Sample Speed
8
10
SYSCTL_RCGC0_ADC0SPD_125K
125K samples/second
0x0
SYSCTL_RCGC0_ADC0SPD_250K
250K samples/second
0x1
SYSCTL_RCGC0_ADC0SPD_500K
500K samples/second
0x2
SYSCTL_RCGC0_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_RCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_RCGC0_ADC1SPD
ADC1 Sample Speed
10
12
SYSCTL_RCGC0_ADC1SPD_125K
125K samples/second
0x0
SYSCTL_RCGC0_ADC1SPD_250K
250K samples/second
0x1
SYSCTL_RCGC0_ADC1SPD_500K
500K samples/second
0x2
SYSCTL_RCGC0_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_RCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_RCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_RCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_RCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_RCGC0_WDT1
WDT1 Clock Gating Control
28
29
RCGC1
Run Mode Clock Gating Control Register 1
0x104
-1
read-write
n
0x0
0x0
SYSCTL_RCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_RCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_RCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_RCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_RCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_RCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_RCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_RCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_RCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_RCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_RCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_RCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_RCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_RCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_RCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_RCGC1_UART2
UART2 Clock Gating Control
2
3
RCGC2
Run Mode Clock Gating Control Register 2
0x108
-1
read-write
n
0x0
0x0
SYSCTL_RCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_RCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_RCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_RCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_RCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_RCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_RCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_RCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_RCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_RCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_RCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_RCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_RCGC2_USB0
USB0 Clock Gating Control
16
17
RESC
Reset Cause
0x5C
-1
read-write
n
0x0
0x0
SYSCTL_RESC_BOR
Brown-Out Reset
2
3
SYSCTL_RESC_EXT
External Reset
0
1
SYSCTL_RESC_MOSCFAIL
MOSC Failure Reset
16
17
SYSCTL_RESC_POR
Power-On Reset
1
2
SYSCTL_RESC_SW
Software Reset
4
5
SYSCTL_RESC_WDT0
Watchdog Timer 0 Reset
3
4
SYSCTL_RESC_WDT1
Watchdog Timer 1 Reset
5
6
RIS
Raw Interrupt Status
0x50
-1
read-write
n
0x0
0x0
SYSCTL_RIS_BORRIS
Brown-Out Reset Raw Interrupt Status
1
2
SYSCTL_RIS_MOSCPUPRIS
MOSC Power Up Raw Interrupt Status
8
9
SYSCTL_RIS_PLLLRIS
PLL Lock Raw Interrupt Status
6
7
SYSCTL_RIS_USBPLLLRIS
USB PLL Lock Raw Interrupt Status
7
8
SCGC0
Sleep Mode Clock Gating Control Register 0
0x110
-1
read-write
n
0x0
0x0
SYSCTL_SCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_SCGC0_ADC0SPD
ADC0 Sample Speed
8
10
SYSCTL_SCGC0_ADC0SPD_125K
125K samples/second
0x0
SYSCTL_SCGC0_ADC0SPD_250K
250K samples/second
0x1
SYSCTL_SCGC0_ADC0SPD_500K
500K samples/second
0x2
SYSCTL_SCGC0_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_SCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_SCGC0_ADC1SPD
ADC1 Sample Speed
10
12
SYSCTL_SCGC0_ADC1SPD_125K
125K samples/second
0x0
SYSCTL_SCGC0_ADC1SPD_250K
250K samples/second
0x1
SYSCTL_SCGC0_ADC1SPD_500K
500K samples/second
0x2
SYSCTL_SCGC0_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_SCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_SCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_SCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_SCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_SCGC0_WDT1
WDT1 Clock Gating Control
28
29
SCGC1
Sleep Mode Clock Gating Control Register 1
0x114
-1
read-write
n
0x0
0x0
SYSCTL_SCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_SCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_SCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_SCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_SCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_SCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_SCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_SCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_SCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_SCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_SCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_SCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_SCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_SCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_SCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_SCGC1_UART2
UART2 Clock Gating Control
2
3
SCGC2
Sleep Mode Clock Gating Control Register 2
0x118
-1
read-write
n
0x0
0x0
SYSCTL_SCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_SCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_SCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_SCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_SCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_SCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_SCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_SCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_SCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_SCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_SCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_SCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_SCGC2_USB0
USB0 Clock Gating Control
16
17
SRCR0
Software Reset Control 0
0x40
-1
read-write
n
0x0
0x0
SYSCTL_SRCR0_ADC0
ADC0 Reset Control
16
17
SYSCTL_SRCR0_ADC1
ADC1 Reset Control
17
18
SYSCTL_SRCR0_CAN0
CAN0 Reset Control
24
25
SYSCTL_SRCR0_CAN1
CAN1 Reset Control
25
26
SYSCTL_SRCR0_HIB
HIB Reset Control
6
7
SYSCTL_SRCR0_WDT0
WDT0 Reset Control
3
4
SYSCTL_SRCR0_WDT1
WDT1 Reset Control
28
29
SRCR1
Software Reset Control 1
0x44
-1
read-write
n
0x0
0x0
SYSCTL_SRCR1_COMP0
Analog Comp 0 Reset Control
24
25
SYSCTL_SRCR1_COMP1
Analog Comp 1 Reset Control
25
26
SYSCTL_SRCR1_I2C0
I2C0 Reset Control
12
13
SYSCTL_SRCR1_I2C1
I2C1 Reset Control
14
15
SYSCTL_SRCR1_I2S0
I2S0 Reset Control
28
29
SYSCTL_SRCR1_QEI0
QEI0 Reset Control
8
9
SYSCTL_SRCR1_QEI1
QEI1 Reset Control
9
10
SYSCTL_SRCR1_SSI0
SSI0 Reset Control
4
5
SYSCTL_SRCR1_SSI1
SSI1 Reset Control
5
6
SYSCTL_SRCR1_TIMER0
Timer 0 Reset Control
16
17
SYSCTL_SRCR1_TIMER1
Timer 1 Reset Control
17
18
SYSCTL_SRCR1_TIMER2
Timer 2 Reset Control
18
19
SYSCTL_SRCR1_TIMER3
Timer 3 Reset Control
19
20
SYSCTL_SRCR1_UART0
UART0 Reset Control
0
1
SYSCTL_SRCR1_UART1
UART1 Reset Control
1
2
SYSCTL_SRCR1_UART2
UART2 Reset Control
2
3
SRCR2
Software Reset Control 2
0x48
-1
read-write
n
0x0
0x0
SYSCTL_SRCR2_EMAC0
MAC0 Reset Control
28
29
SYSCTL_SRCR2_EPHY0
PHY0 Reset Control
30
31
SYSCTL_SRCR2_GPIOA
Port A Reset Control
0
1
SYSCTL_SRCR2_GPIOB
Port B Reset Control
1
2
SYSCTL_SRCR2_GPIOC
Port C Reset Control
2
3
SYSCTL_SRCR2_GPIOD
Port D Reset Control
3
4
SYSCTL_SRCR2_GPIOE
Port E Reset Control
4
5
SYSCTL_SRCR2_GPIOF
Port F Reset Control
5
6
SYSCTL_SRCR2_GPIOG
Port G Reset Control
6
7
SYSCTL_SRCR2_GPIOH
Port H Reset Control
7
8
SYSCTL_SRCR2_GPIOJ
Port J Reset Control
8
9
SYSCTL_SRCR2_UDMA
Micro-DMA Reset Control
13
14
SYSCTL_SRCR2_USB0
USB0 Reset Control
16
17
SYSCTLDC0
Device Capabilities 0
0x8
read-write
n
0x0
0x0
SYSCTL_DC0_FLASHSZ
Flash Size
0
16
SYSCTL_DC0_FLASHSZ_256K
256 KB of Flash
0x7f
SYSCTL_DC0_SRAMSZ
SRAM Size
16
32
SYSCTL_DC0_SRAMSZ_64KB
64 KB of SRAM
0xff
SYSCTLDC1
Device Capabilities 1
0x10
read-write
n
0x0
0x0
SYSCTL_DC1_ADC0
ADC Module 0 Present
16
17
SYSCTL_DC1_ADC0SPD
Max ADC0 Speed
8
10
SYSCTL_DC1_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_DC1_ADC1
ADC Module 1 Present
17
18
SYSCTL_DC1_ADC1SPD
Max ADC1 Speed
10
12
SYSCTL_DC1_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_DC1_CAN0
CAN Module 0 Present
24
25
SYSCTL_DC1_CAN1
CAN Module 1 Present
25
26
SYSCTL_DC1_HIB
Hibernation Module Present
6
7
SYSCTL_DC1_JTAG
JTAG Present
0
1
SYSCTL_DC1_MINSYSDIV
System Clock Divider
12
16
SYSCTL_DC1_MINSYSDIV_100
Divide VCO (400MHZ) by 5 minimum
0x1
SYSCTL_DC1_MINSYSDIV_66
Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum
0x2
SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x3
SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
0x7
SYSCTL_DC1_MINSYSDIV_20
Specifies a 20-MHz clock with a PLL divider of 10
0x9
SYSCTL_DC1_MPU
MPU Present
7
8
SYSCTL_DC1_PLL
PLL Present
4
5
SYSCTL_DC1_SWD
SWD Present
1
2
SYSCTL_DC1_SWO
SWO Trace Port Present
2
3
SYSCTL_DC1_TEMP
Temp Sensor Present
5
6
SYSCTL_DC1_WDT0
Watchdog Timer 0 Present
3
4
SYSCTL_DC1_WDT1
Watchdog Timer1 Present
28
29
SYSCTLDC2
Device Capabilities 2
0x14
read-write
n
0x0
0x0
SYSCTL_DC2_COMP0
Analog Comparator 0 Present
24
25
SYSCTL_DC2_COMP1
Analog Comparator 1 Present
25
26
SYSCTL_DC2_I2C0
I2C Module 0 Present
12
13
SYSCTL_DC2_I2C1
I2C Module 1 Present
14
15
SYSCTL_DC2_I2S0
I2S Module 0 Present
28
29
SYSCTL_DC2_QEI0
QEI Module 0 Present
8
9
SYSCTL_DC2_QEI1
QEI Module 1 Present
9
10
SYSCTL_DC2_SSI0
SSI Module 0 Present
4
5
SYSCTL_DC2_SSI1
SSI Module 1 Present
5
6
SYSCTL_DC2_TIMER0
Timer Module 0 Present
16
17
SYSCTL_DC2_TIMER1
Timer Module 1 Present
17
18
SYSCTL_DC2_TIMER2
Timer Module 2 Present
18
19
SYSCTL_DC2_TIMER3
Timer Module 3 Present
19
20
SYSCTL_DC2_UART0
UART Module 0 Present
0
1
SYSCTL_DC2_UART1
UART Module 1 Present
1
2
SYSCTL_DC2_UART2
UART Module 2 Present
2
3
SYSCTLDC3
Device Capabilities 3
0x18
read-write
n
0x0
0x0
SYSCTL_DC3_32KHZ
32KHz Input Clock Available
31
32
SYSCTL_DC3_ADC0AIN0
ADC Module 0 AIN0 Pin Present
16
17
SYSCTL_DC3_ADC0AIN1
ADC Module 0 AIN1 Pin Present
17
18
SYSCTL_DC3_ADC0AIN2
ADC Module 0 AIN2 Pin Present
18
19
SYSCTL_DC3_ADC0AIN3
ADC Module 0 AIN3 Pin Present
19
20
SYSCTL_DC3_ADC0AIN4
ADC Module 0 AIN4 Pin Present
20
21
SYSCTL_DC3_ADC0AIN5
ADC Module 0 AIN5 Pin Present
21
22
SYSCTL_DC3_ADC0AIN6
ADC Module 0 AIN6 Pin Present
22
23
SYSCTL_DC3_ADC0AIN7
ADC Module 0 AIN7 Pin Present
23
24
SYSCTL_DC3_C0MINUS
C0- Pin Present
6
7
SYSCTL_DC3_C0O
C0o Pin Present
8
9
SYSCTL_DC3_C0PLUS
C0+ Pin Present
7
8
SYSCTL_DC3_C1MINUS
C1- Pin Present
9
10
SYSCTL_DC3_C1O
C1o Pin Present
11
12
SYSCTL_DC3_C1PLUS
C1+ Pin Present
10
11
SYSCTL_DC3_CCP0
CCP0 Pin Present
24
25
SYSCTL_DC3_CCP1
CCP1 Pin Present
25
26
SYSCTL_DC3_CCP2
CCP2 Pin Present
26
27
SYSCTL_DC3_CCP3
CCP3 Pin Present
27
28
SYSCTL_DC3_CCP4
CCP4 Pin Present
28
29
SYSCTL_DC3_CCP5
CCP5 Pin Present
29
30
SYSCTL_DC3_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC3_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC3_PWM2
PWM2 Pin Present
2
3
SYSCTL_DC3_PWM3
PWM3 Pin Present
3
4
SYSCTL_DC3_PWM4
PWM4 Pin Present
4
5
SYSCTL_DC3_PWM5
PWM5 Pin Present
5
6
SYSCTL_DC3_PWMFAULT
PWM Fault Pin Present
15
16
SYSCTLDC4
Device Capabilities 4
0x1C
read-write
n
0x0
0x0
SYSCTL_DC4_CCP6
CCP6 Pin Present
14
15
SYSCTL_DC4_CCP7
CCP7 Pin Present
15
16
SYSCTL_DC4_E1588
1588 Capable
24
25
SYSCTL_DC4_EMAC0
Ethernet MAC Layer 0 Present
28
29
SYSCTL_DC4_EPHY0
Ethernet PHY Layer 0 Present
30
31
SYSCTL_DC4_GPIOA
GPIO Port A Present
0
1
SYSCTL_DC4_GPIOB
GPIO Port B Present
1
2
SYSCTL_DC4_GPIOC
GPIO Port C Present
2
3
SYSCTL_DC4_GPIOD
GPIO Port D Present
3
4
SYSCTL_DC4_GPIOE
GPIO Port E Present
4
5
SYSCTL_DC4_GPIOF
GPIO Port F Present
5
6
SYSCTL_DC4_GPIOG
GPIO Port G Present
6
7
SYSCTL_DC4_GPIOH
GPIO Port H Present
7
8
SYSCTL_DC4_GPIOJ
GPIO Port J Present
8
9
SYSCTL_DC4_PICAL
PIOSC Calibrate
18
19
SYSCTL_DC4_ROM
Internal Code ROM Present
12
13
SYSCTL_DC4_UDMA
Micro-DMA Module Present
13
14
SYSCTLDC5
Device Capabilities 5
0x20
read-write
n
0x0
0x0
SYSCTL_DC5_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC5_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC5_PWM2
PWM2 Pin Present
2
3
SYSCTL_DC5_PWM3
PWM3 Pin Present
3
4
SYSCTL_DC5_PWM4
PWM4 Pin Present
4
5
SYSCTL_DC5_PWM5
PWM5 Pin Present
5
6
SYSCTL_DC5_PWMEFLT
PWM Extended Fault Active
21
22
SYSCTL_DC5_PWMESYNC
PWM Extended SYNC Active
20
21
SYSCTL_DC5_PWMFAULT0
PWM Fault 0 Pin Present
24
25
SYSCTL_DC5_PWMFAULT1
PWM Fault 1 Pin Present
25
26
SYSCTL_DC5_PWMFAULT2
PWM Fault 2 Pin Present
26
27
SYSCTL_DC5_PWMFAULT3
PWM Fault 3 Pin Present
27
28
SYSCTLDC6
Device Capabilities 6
0x24
read-write
n
0x0
0x0
SYSCTL_DC6_USB0
USB Module 0 Present
0
2
SYSCTL_DC6_USB0_OTG
USB0 is OTG
0x3
SYSCTL_DC6_USB0PHY
USB Module 0 PHY Present
4
5
SYSCTLDC7
Device Capabilities 7
0x28
read-write
n
0x0
0x0
SYSCTL_DC7_DMACH0
USB_EP1_RX / UART2_RX
0
1
SYSCTL_DC7_DMACH1
USB_EP1_TX / UART2_TX
1
2
SYSCTL_DC7_DMACH10
SSI0_RX / SSI1_RX
10
11
SYSCTL_DC7_DMACH11
SSI0_TX / SSI1_TX
11
12
SYSCTL_DC7_DMACH12
CAN0_RX / UART2_RX
12
13
SYSCTL_DC7_DMACH13
CAN0_TX / UART2_TX
13
14
SYSCTL_DC7_DMACH14
ADC0_SS0 / Timer2A
14
15
SYSCTL_DC7_DMACH15
ADC0_SS1 / Timer2B
15
16
SYSCTL_DC7_DMACH16
ADC0_SS2
16
17
SYSCTL_DC7_DMACH17
ADC0_SS3
17
18
SYSCTL_DC7_DMACH18
Timer0A / Timer1A
18
19
SYSCTL_DC7_DMACH19
Timer0B / Timer1B
19
20
SYSCTL_DC7_DMACH2
USB_EP2_RX / Timer3A
2
3
SYSCTL_DC7_DMACH20
Timer1A / EPI0_NBRFIFO
20
21
SYSCTL_DC7_DMACH21
Timer1B / EPI0_WFIFO
21
22
SYSCTL_DC7_DMACH22
UART1_RX / CAN2_RX
22
23
SYSCTL_DC7_DMACH23
UART1_TX / CAN2_TX
23
24
SYSCTL_DC7_DMACH24
SSI1_RX / ADC1_SS0
24
25
SYSCTL_DC7_DMACH25
SSI1_TX / ADC1_SS1
25
26
SYSCTL_DC7_DMACH26
CAN1_RX / ADC1_SS2
26
27
SYSCTL_DC7_DMACH27
CAN1_TX / ADC1_SS3
27
28
SYSCTL_DC7_DMACH28
I2S0_RX / CAN1_RX
28
29
SYSCTL_DC7_DMACH29
I2S0_TX / CAN1_TX
29
30
SYSCTL_DC7_DMACH3
USB_EP2_TX / Timer3B
3
4
SYSCTL_DC7_DMACH30
SW
30
31
SYSCTL_DC7_DMACH4
USB_EP3_RX / Timer2A
4
5
SYSCTL_DC7_DMACH5
USB_EP3_TX / Timer2B
5
6
SYSCTL_DC7_DMACH6
ETH_RX / Timer2A
6
7
SYSCTL_DC7_DMACH7
ETH_TX / Timer2B
7
8
SYSCTL_DC7_DMACH8
UART0_RX / UART1_RX
8
9
SYSCTL_DC7_DMACH9
UART0_TX / UART1_TX
9
10
SYSCTLDC8
Device Capabilities 8 ADC Channels
0x2C
read-write
n
0x0
0x0
SYSCTL_DC8_ADC0AIN0
ADC Module 0 AIN0 Pin Present
0
1
SYSCTL_DC8_ADC0AIN1
ADC Module 0 AIN1 Pin Present
1
2
SYSCTL_DC8_ADC0AIN10
ADC Module 0 AIN10 Pin Present
10
11
SYSCTL_DC8_ADC0AIN11
ADC Module 0 AIN11 Pin Present
11
12
SYSCTL_DC8_ADC0AIN12
ADC Module 0 AIN12 Pin Present
12
13
SYSCTL_DC8_ADC0AIN13
ADC Module 0 AIN13 Pin Present
13
14
SYSCTL_DC8_ADC0AIN14
ADC Module 0 AIN14 Pin Present
14
15
SYSCTL_DC8_ADC0AIN15
ADC Module 0 AIN15 Pin Present
15
16
SYSCTL_DC8_ADC0AIN2
ADC Module 0 AIN2 Pin Present
2
3
SYSCTL_DC8_ADC0AIN3
ADC Module 0 AIN3 Pin Present
3
4
SYSCTL_DC8_ADC0AIN4
ADC Module 0 AIN4 Pin Present
4
5
SYSCTL_DC8_ADC0AIN5
ADC Module 0 AIN5 Pin Present
5
6
SYSCTL_DC8_ADC0AIN6
ADC Module 0 AIN6 Pin Present
6
7
SYSCTL_DC8_ADC0AIN7
ADC Module 0 AIN7 Pin Present
7
8
SYSCTL_DC8_ADC0AIN8
ADC Module 0 AIN8 Pin Present
8
9
SYSCTL_DC8_ADC0AIN9
ADC Module 0 AIN9 Pin Present
9
10
SYSCTL_DC8_ADC1AIN0
ADC Module 1 AIN0 Pin Present
16
17
SYSCTL_DC8_ADC1AIN1
ADC Module 1 AIN1 Pin Present
17
18
SYSCTL_DC8_ADC1AIN10
ADC Module 1 AIN10 Pin Present
26
27
SYSCTL_DC8_ADC1AIN11
ADC Module 1 AIN11 Pin Present
27
28
SYSCTL_DC8_ADC1AIN12
ADC Module 1 AIN12 Pin Present
28
29
SYSCTL_DC8_ADC1AIN13
ADC Module 1 AIN13 Pin Present
29
30
SYSCTL_DC8_ADC1AIN14
ADC Module 1 AIN14 Pin Present
30
31
SYSCTL_DC8_ADC1AIN15
ADC Module 1 AIN15 Pin Present
31
32
SYSCTL_DC8_ADC1AIN2
ADC Module 1 AIN2 Pin Present
18
19
SYSCTL_DC8_ADC1AIN3
ADC Module 1 AIN3 Pin Present
19
20
SYSCTL_DC8_ADC1AIN4
ADC Module 1 AIN4 Pin Present
20
21
SYSCTL_DC8_ADC1AIN5
ADC Module 1 AIN5 Pin Present
21
22
SYSCTL_DC8_ADC1AIN6
ADC Module 1 AIN6 Pin Present
22
23
SYSCTL_DC8_ADC1AIN7
ADC Module 1 AIN7 Pin Present
23
24
SYSCTL_DC8_ADC1AIN8
ADC Module 1 AIN8 Pin Present
24
25
SYSCTL_DC8_ADC1AIN9
ADC Module 1 AIN9 Pin Present
25
26
SYSCTLDC9
Device Capabilities 9 ADC Digital Comparators
0x190
read-write
n
0x0
0x0
SYSCTL_DC9_ADC0DC0
ADC0 DC0 Present
0
1
SYSCTL_DC9_ADC0DC1
ADC0 DC1 Present
1
2
SYSCTL_DC9_ADC0DC2
ADC0 DC2 Present
2
3
SYSCTL_DC9_ADC0DC3
ADC0 DC3 Present
3
4
SYSCTL_DC9_ADC0DC4
ADC0 DC4 Present
4
5
SYSCTL_DC9_ADC0DC5
ADC0 DC5 Present
5
6
SYSCTL_DC9_ADC0DC6
ADC0 DC6 Present
6
7
SYSCTL_DC9_ADC0DC7
ADC0 DC7 Present
7
8
SYSCTL_DC9_ADC1DC0
ADC1 DC0 Present
16
17
SYSCTL_DC9_ADC1DC1
ADC1 DC1 Present
17
18
SYSCTL_DC9_ADC1DC2
ADC1 DC2 Present
18
19
SYSCTL_DC9_ADC1DC3
ADC1 DC3 Present
19
20
SYSCTL_DC9_ADC1DC4
ADC1 DC4 Present
20
21
SYSCTL_DC9_ADC1DC5
ADC1 DC5 Present
21
22
SYSCTL_DC9_ADC1DC6
ADC1 DC6 Present
22
23
SYSCTL_DC9_ADC1DC7
ADC1 DC7 Present
23
24
SYSCTLDCGC0
Deep Sleep Mode Clock Gating Control Register 0
0x120
read-write
n
0x0
0x0
SYSCTL_DCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_DCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_DCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_DCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_DCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_DCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_DCGC0_WDT1
WDT1 Clock Gating Control
28
29
SYSCTLDCGC1
Deep-Sleep Mode Clock Gating Control Register 1
0x124
read-write
n
0x0
0x0
SYSCTL_DCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_DCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_DCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_DCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_DCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_DCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_DCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_DCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_DCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_DCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_DCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_DCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_DCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_DCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_DCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_DCGC1_UART2
UART2 Clock Gating Control
2
3
SYSCTLDCGC2
Deep Sleep Mode Clock Gating Control Register 2
0x128
read-write
n
0x0
0x0
SYSCTL_DCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_DCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_DCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_DCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_DCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_DCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_DCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_DCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_DCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_DCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_DCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_DCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_DCGC2_USB0
USB0 Clock Gating Control
16
17
SYSCTLDID0
Device Identification 0
0x0
read-write
n
0x0
0x0
SYSCTL_DID0_CLASS
Device Class
16
24
SYSCTL_DID0_CLASS_TEMPEST
Stellaris(R) Tempest-class microcontrollers
0x4
SYSCTL_DID0_MAJ
Major Revision
8
16
SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x0
SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x1
SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
0x2
SYSCTL_DID0_MIN
Minor Revision
0
8
SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x0
SYSCTL_DID0_MIN_1
First metal layer change
0x1
SYSCTL_DID0_MIN_2
Second metal layer change
0x2
SYSCTL_DID0_VER
DID0 Version
28
31
SYSCTL_DID0_VER_1
Second version of the DID0 register format
0x1
SYSCTLDID1
Device Identification 1
0x4
read-write
n
0x0
0x0
SYSCTL_DID1_FAM
Family
24
28
SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
0x0
SYSCTL_DID1_PINCNT
Package Pin Count
13
16
SYSCTL_DID1_PINCNT_100
100-pin package
0x2
SYSCTL_DID1_PKG
Package Type
3
5
SYSCTL_DID1_PKG_SOIC
SOIC package
0x0
SYSCTL_DID1_PKG_QFP
LQFP package
0x1
SYSCTL_DID1_PKG_BGA
BGA package
0x2
SYSCTL_DID1_PRTNO
Part Number
16
24
SYSCTL_DID1_PRTNO_9997
LM3S9997
0x20
SYSCTL_DID1_QUAL
Qualification Status
0
2
SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x0
SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x1
SYSCTL_DID1_QUAL_FQ
Fully Qualified
0x2
SYSCTL_DID1_ROHS
RoHS-Compliance
2
3
SYSCTL_DID1_TEMP
Temperature Range
5
8
SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x0
SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x1
SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
0x2
SYSCTL_DID1_VER
DID1 Version
28
32
SYSCTL_DID1_VER_1
Second version of the DID1 register format
0x1
SYSCTLDSLPCLKCFG
Deep Sleep Clock Configuration
0x144
read-write
n
0x0
0x0
SYSCTL_DSLPCLKCFG_D
Divider Field Override
23
29
SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x0
SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x1
SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x10
SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x11
SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x12
SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x13
SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x14
SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x15
SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x16
SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x17
SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x18
SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x19
SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1a
SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1b
SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1c
SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1d
SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1e
SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x1f
SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x2
SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x20
SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x21
SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x22
SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x23
SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x24
SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x25
SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x26
SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x27
SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x28
SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x29
SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2a
SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2b
SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2c
SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2d
SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2e
SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x2f
SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x3
SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x30
SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x31
SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x32
SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x33
SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x34
SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x35
SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x36
SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x37
SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x38
SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x39
SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3a
SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3b
SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3c
SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3d
SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3e
SYSCTL_DSLPCLKCFG_D_64
System clock /64
0x3f
SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x4
SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x5
SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x6
SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x7
SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x8
SYSCTL_DSLPCLKCFG_D_10
System clock /10
0x9
SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xa
SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xb
SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xc
SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xd
SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xe
SYSCTL_DSLPCLKCFG_D_16
System clock /16
0xf
SYSCTL_DSLPCLKCFG_O
Clock Source
4
7
SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x0
SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x1
SYSCTL_DSLPCLKCFG_O_30
30 kHz
0x3
SYSCTL_DSLPCLKCFG_O_32
32.768 kHz
0x7
SYSCTLGPIOHBCTL
GPIO High-Performance Bus Control
0x6C
read-write
n
0x0
0x0
SYSCTL_GPIOHBCTL_PORTA
Port A Advanced High-Performance Bus
0
1
SYSCTL_GPIOHBCTL_PORTB
Port B Advanced High-Performance Bus
1
2
SYSCTL_GPIOHBCTL_PORTC
Port C Advanced High-Performance Bus
2
3
SYSCTL_GPIOHBCTL_PORTD
Port D Advanced High-Performance Bus
3
4
SYSCTL_GPIOHBCTL_PORTE
Port E Advanced High-Performance Bus
4
5
SYSCTL_GPIOHBCTL_PORTF
Port F Advanced High-Performance Bus
5
6
SYSCTL_GPIOHBCTL_PORTG
Port G Advanced High-Performance Bus
6
7
SYSCTL_GPIOHBCTL_PORTH
Port H Advanced High-Performance Bus
7
8
SYSCTL_GPIOHBCTL_PORTJ
Port J Advanced High-Performance Bus
8
9
SYSCTLI2SMCLKCFG
I2S MCLK Configuration
0x170
read-write
n
0x0
0x0
SYSCTL_I2SMCLKCFG_RXEN
RX Clock Enable
31
32
SYSCTL_I2SMCLKCFG_RXF
RX Clock Fractional Input
16
20
SYSCTL_I2SMCLKCFG_RXI
RX Clock Integer Input
20
30
SYSCTL_I2SMCLKCFG_TXEN
TX Clock Enable
15
16
SYSCTL_I2SMCLKCFG_TXF
TX Clock Fractional Input
0
4
SYSCTL_I2SMCLKCFG_TXI
TX Clock Integer Input
4
14
SYSCTLIMC
Interrupt Mask Control
0x54
read-write
n
0x0
0x0
SYSCTL_IMC_BORIM
Brown-Out Reset Interrupt Mask
1
2
SYSCTL_IMC_MOSCPUPIM
MOSC Power Up Interrupt Mask
8
9
SYSCTL_IMC_PLLLIM
PLL Lock Interrupt Mask
6
7
SYSCTL_IMC_USBPLLLIM
USB PLL Lock Interrupt Mask
7
8
SYSCTLMISC
Masked Interrupt Status and Clear
0x58
read-write
n
0x0
0x0
SYSCTL_MISC_BORMIS
BOR Masked Interrupt Status
1
2
SYSCTL_MISC_MOSCPUPMIS
MOSC Power Up Masked Interrupt Status
8
9
SYSCTL_MISC_PLLLMIS
PLL Lock Masked Interrupt Status
6
7
SYSCTL_MISC_USBPLLLMIS
USB PLL Lock Masked Interrupt Status
7
8
SYSCTLMOSCCTL
Main Oscillator Control
0x7C
read-write
n
0x0
0x0
SYSCTL_MOSCCTL_CVAL
Clock Validation for MOSC
0
1
SYSCTLNVMSTAT
Non-Volatile Memory Information
0x1A0
read-write
n
0x0
0x0
SYSCTL_NVMSTAT_FWB
32 Word Flash Write Buffer Active
0
1
SYSCTLPBORCTL
Brown-Out Reset Control
0x30
read-write
n
0x0
0x0
SYSCTL_PBORCTL_BORIOR
BOR Interrupt or Reset
1
2
SYSCTLPIOSCCAL
Precision Internal Oscillator Calibration
0x150
read-write
n
0x0
0x0
SYSCTL_PIOSCCAL_CAL
Start Calibration
9
10
SYSCTL_PIOSCCAL_UPDATE
Update Trim
8
9
SYSCTL_PIOSCCAL_UT
User Trim Value
0
7
SYSCTL_PIOSCCAL_UTEN
Use User Trim Value
31
32
SYSCTLPIOSCSTAT
Precision Internal Oscillator Statistics
0x154
read-write
n
0x0
0x0
SYSCTL_PIOSCSTAT_CR
Calibration Result
8
10
SYSCTL_PIOSCSTAT_CRNONE
Calibration has not been attempted
0x0
SYSCTL_PIOSCSTAT_CRPASS
The last calibration operation completed to meet 1% accuracy
0x1
SYSCTL_PIOSCSTAT_CRFAIL
The last calibration operation failed to meet 1% accuracy
0x2
SYSCTL_PIOSCSTAT_CT
Calibration Trim Value
0
7
SYSCTL_PIOSCSTAT_DT
Default Trim Value
16
23
SYSCTLPLLCFG
XTAL to PLL Translation
0x64
read-write
n
0x0
0x0
SYSCTL_PLLCFG_F
PLL F Value
5
14
SYSCTL_PLLCFG_R
PLL R Value
0
5
SYSCTLRCC
Run-Mode Clock Configuration
0x60
read-write
n
0x0
0x0
SYSCTL_RCC_ACG
Auto Clock Gating
27
28
SYSCTL_RCC_BYPASS
PLL Bypass
11
12
SYSCTL_RCC_IOSCDIS
Internal Oscillator Disable
1
2
SYSCTL_RCC_MOSCDIS
Main Oscillator Disable
0
1
SYSCTL_RCC_OSCSRC
Oscillator Source
4
6
SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x0
SYSCTL_RCC_OSCSRC_INT
IOSC
0x1
SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x2
SYSCTL_RCC_OSCSRC_30
30 kHz
0x3
SYSCTL_RCC_PWMDIV
PWM Unit Clock Divisor
17
20
SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x0
SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x1
SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x2
SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x3
SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x4
SYSCTL_RCC_PWMDIV_64
PWM clock /64
0x5
SYSCTL_RCC_PWRDN
PLL Power Down
13
14
SYSCTL_RCC_SYSDIV
System Clock Divisor
23
27
SYSCTL_RCC_USEPWMDIV
Enable PWM Clock Divisor
20
21
SYSCTL_RCC_USESYSDIV
Enable System Clock Divider
22
23
SYSCTL_RCC_XTAL
Crystal Value
6
11
SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x0
SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x1
SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x10
SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x11
SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x12
SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x13
SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x14
SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x15
SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
0x16
SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x2
SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x3
SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x4
SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x5
SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x6
SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x7
SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x8
SYSCTL_RCC_XTAL_5MHZ
5 MHz
0x9
SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xa
SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xb
SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xc
SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xd
SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xe
SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0xf
SYSCTLRCC2
Run-Mode Clock Configuration 2
0x70
read-write
n
0x0
0x0
SYSCTL_RCC2_BYPASS2
PLL Bypass 2
11
12
SYSCTL_RCC2_DIV400
Divide PLL as 400 MHz vs. 200 MHz
30
31
SYSCTL_RCC2_OSCSRC2
Oscillator Source 2
4
7
SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x0
SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x1
SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x2
SYSCTL_RCC2_OSCSRC2_30
30 kHz
0x3
SYSCTL_RCC2_OSCSRC2_419
4.194304 MHz
0x6
SYSCTL_RCC2_OSCSRC2_32
32.768 kHz
0x7
SYSCTL_RCC2_PWRDN2
Power-Down PLL 2
13
14
SYSCTL_RCC2_SYSDIV2
System Clock Divisor 2
23
29
SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x1
SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x10
SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x11
SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x12
SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x13
SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x14
SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x15
SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x16
SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x17
SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x18
SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x19
SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1a
SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1b
SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1c
SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1d
SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1e
SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x1f
SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x2
SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x20
SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x21
SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x22
SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x23
SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x24
SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x25
SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x26
SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x27
SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x28
SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x29
SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2a
SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2b
SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2c
SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2d
SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2e
SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x2f
SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x3
SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x30
SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x31
SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x32
SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x33
SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x34
SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x35
SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x36
SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x37
SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x38
SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x39
SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3a
SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3b
SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3c
SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3d
SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3e
SYSCTL_RCC2_SYSDIV2_64
System clock /64
0x3f
SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x4
SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x5
SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x6
SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x7
SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x8
SYSCTL_RCC2_SYSDIV2_10
System clock /10
0x9
SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xa
SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xb
SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xc
SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xd
SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xe
SYSCTL_RCC2_SYSDIV2_16
System clock /16
0xf
SYSCTL_RCC2_SYSDIV2LSB
Additional LSB for SYSDIV2
22
23
SYSCTL_RCC2_USBPWRDN
Power-Down USB PLL
14
15
SYSCTL_RCC2_USERCC2
Use RCC2
31
32
SYSCTLRCGC0
Run Mode Clock Gating Control Register 0
0x100
read-write
n
0x0
0x0
SYSCTL_RCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_RCGC0_ADC0SPD
ADC0 Sample Speed
8
10
SYSCTL_RCGC0_ADC0SPD_125K
125K samples/second
0x0
SYSCTL_RCGC0_ADC0SPD_250K
250K samples/second
0x1
SYSCTL_RCGC0_ADC0SPD_500K
500K samples/second
0x2
SYSCTL_RCGC0_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_RCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_RCGC0_ADC1SPD
ADC1 Sample Speed
10
12
SYSCTL_RCGC0_ADC1SPD_125K
125K samples/second
0x0
SYSCTL_RCGC0_ADC1SPD_250K
250K samples/second
0x1
SYSCTL_RCGC0_ADC1SPD_500K
500K samples/second
0x2
SYSCTL_RCGC0_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_RCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_RCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_RCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_RCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_RCGC0_WDT1
WDT1 Clock Gating Control
28
29
SYSCTLRCGC1
Run Mode Clock Gating Control Register 1
0x104
read-write
n
0x0
0x0
SYSCTL_RCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_RCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_RCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_RCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_RCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_RCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_RCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_RCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_RCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_RCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_RCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_RCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_RCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_RCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_RCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_RCGC1_UART2
UART2 Clock Gating Control
2
3
SYSCTLRCGC2
Run Mode Clock Gating Control Register 2
0x108
read-write
n
0x0
0x0
SYSCTL_RCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_RCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_RCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_RCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_RCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_RCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_RCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_RCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_RCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_RCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_RCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_RCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_RCGC2_USB0
USB0 Clock Gating Control
16
17
SYSCTLRESC
Reset Cause
0x5C
read-write
n
0x0
0x0
SYSCTL_RESC_BOR
Brown-Out Reset
2
3
SYSCTL_RESC_EXT
External Reset
0
1
SYSCTL_RESC_MOSCFAIL
MOSC Failure Reset
16
17
SYSCTL_RESC_POR
Power-On Reset
1
2
SYSCTL_RESC_SW
Software Reset
4
5
SYSCTL_RESC_WDT0
Watchdog Timer 0 Reset
3
4
SYSCTL_RESC_WDT1
Watchdog Timer 1 Reset
5
6
SYSCTLRIS
Raw Interrupt Status
0x50
read-write
n
0x0
0x0
SYSCTL_RIS_BORRIS
Brown-Out Reset Raw Interrupt Status
1
2
SYSCTL_RIS_MOSCPUPRIS
MOSC Power Up Raw Interrupt Status
8
9
SYSCTL_RIS_PLLLRIS
PLL Lock Raw Interrupt Status
6
7
SYSCTL_RIS_USBPLLLRIS
USB PLL Lock Raw Interrupt Status
7
8
SYSCTLSCGC0
Sleep Mode Clock Gating Control Register 0
0x110
read-write
n
0x0
0x0
SYSCTL_SCGC0_ADC0
ADC0 Clock Gating Control
16
17
SYSCTL_SCGC0_ADC0SPD
ADC0 Sample Speed
8
10
SYSCTL_SCGC0_ADC0SPD_125K
125K samples/second
0x0
SYSCTL_SCGC0_ADC0SPD_250K
250K samples/second
0x1
SYSCTL_SCGC0_ADC0SPD_500K
500K samples/second
0x2
SYSCTL_SCGC0_ADC0SPD_1M
1M samples/second
0x3
SYSCTL_SCGC0_ADC1
ADC1 Clock Gating Control
17
18
SYSCTL_SCGC0_ADC1SPD
ADC1 Sample Speed
10
12
SYSCTL_SCGC0_ADC1SPD_125K
125K samples/second
0x0
SYSCTL_SCGC0_ADC1SPD_250K
250K samples/second
0x1
SYSCTL_SCGC0_ADC1SPD_500K
500K samples/second
0x2
SYSCTL_SCGC0_ADC1SPD_1M
1M samples/second
0x3
SYSCTL_SCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTL_SCGC0_CAN1
CAN1 Clock Gating Control
25
26
SYSCTL_SCGC0_HIB
HIB Clock Gating Control
6
7
SYSCTL_SCGC0_WDT0
WDT0 Clock Gating Control
3
4
SYSCTL_SCGC0_WDT1
WDT1 Clock Gating Control
28
29
SYSCTLSCGC1
Sleep Mode Clock Gating Control Register 1
0x114
read-write
n
0x0
0x0
SYSCTL_SCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_SCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_SCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_SCGC1_I2C1
I2C1 Clock Gating Control
14
15
SYSCTL_SCGC1_I2S0
I2S0 Clock Gating
28
29
SYSCTL_SCGC1_QEI0
QEI0 Clock Gating Control
8
9
SYSCTL_SCGC1_QEI1
QEI1 Clock Gating Control
9
10
SYSCTL_SCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_SCGC1_SSI1
SSI1 Clock Gating Control
5
6
SYSCTL_SCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_SCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_SCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_SCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_SCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTL_SCGC1_UART1
UART1 Clock Gating Control
1
2
SYSCTL_SCGC1_UART2
UART2 Clock Gating Control
2
3
SYSCTLSCGC2
Sleep Mode Clock Gating Control Register 2
0x118
read-write
n
0x0
0x0
SYSCTL_SCGC2_EMAC0
MAC0 Clock Gating Control
28
29
SYSCTL_SCGC2_EPHY0
PHY0 Clock Gating Control
30
31
SYSCTL_SCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_SCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_SCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_SCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_SCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_SCGC2_GPIOF
Port F Clock Gating Control
5
6
SYSCTL_SCGC2_GPIOG
Port G Clock Gating Control
6
7
SYSCTL_SCGC2_GPIOH
Port H Clock Gating Control
7
8
SYSCTL_SCGC2_GPIOJ
Port J Clock Gating Control
8
9
SYSCTL_SCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTL_SCGC2_USB0
USB0 Clock Gating Control
16
17
SYSCTLSRCR0
Software Reset Control 0
0x40
read-write
n
0x0
0x0
SYSCTL_SRCR0_ADC0
ADC0 Reset Control
16
17
SYSCTL_SRCR0_ADC1
ADC1 Reset Control
17
18
SYSCTL_SRCR0_CAN0
CAN0 Reset Control
24
25
SYSCTL_SRCR0_CAN1
CAN1 Reset Control
25
26
SYSCTL_SRCR0_HIB
HIB Reset Control
6
7
SYSCTL_SRCR0_WDT0
WDT0 Reset Control
3
4
SYSCTL_SRCR0_WDT1
WDT1 Reset Control
28
29
SYSCTLSRCR1
Software Reset Control 1
0x44
read-write
n
0x0
0x0
SYSCTL_SRCR1_COMP0
Analog Comp 0 Reset Control
24
25
SYSCTL_SRCR1_COMP1
Analog Comp 1 Reset Control
25
26
SYSCTL_SRCR1_I2C0
I2C0 Reset Control
12
13
SYSCTL_SRCR1_I2C1
I2C1 Reset Control
14
15
SYSCTL_SRCR1_I2S0
I2S0 Reset Control
28
29
SYSCTL_SRCR1_QEI0
QEI0 Reset Control
8
9
SYSCTL_SRCR1_QEI1
QEI1 Reset Control
9
10
SYSCTL_SRCR1_SSI0
SSI0 Reset Control
4
5
SYSCTL_SRCR1_SSI1
SSI1 Reset Control
5
6
SYSCTL_SRCR1_TIMER0
Timer 0 Reset Control
16
17
SYSCTL_SRCR1_TIMER1
Timer 1 Reset Control
17
18
SYSCTL_SRCR1_TIMER2
Timer 2 Reset Control
18
19
SYSCTL_SRCR1_TIMER3
Timer 3 Reset Control
19
20
SYSCTL_SRCR1_UART0
UART0 Reset Control
0
1
SYSCTL_SRCR1_UART1
UART1 Reset Control
1
2
SYSCTL_SRCR1_UART2
UART2 Reset Control
2
3
SYSCTLSRCR2
Software Reset Control 2
0x48
read-write
n
0x0
0x0
SYSCTL_SRCR2_EMAC0
MAC0 Reset Control
28
29
SYSCTL_SRCR2_EPHY0
PHY0 Reset Control
30
31
SYSCTL_SRCR2_GPIOA
Port A Reset Control
0
1
SYSCTL_SRCR2_GPIOB
Port B Reset Control
1
2
SYSCTL_SRCR2_GPIOC
Port C Reset Control
2
3
SYSCTL_SRCR2_GPIOD
Port D Reset Control
3
4
SYSCTL_SRCR2_GPIOE
Port E Reset Control
4
5
SYSCTL_SRCR2_GPIOF
Port F Reset Control
5
6
SYSCTL_SRCR2_GPIOG
Port G Reset Control
6
7
SYSCTL_SRCR2_GPIOH
Port H Reset Control
7
8
SYSCTL_SRCR2_GPIOJ
Port J Reset Control
8
9
SYSCTL_SRCR2_UDMA
Micro-DMA Reset Control
13
14
SYSCTL_SRCR2_USB0
USB0 Reset Control
16
17
TIMER0
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TAPMR
GPTM TimerA Prescale Match
0x40
-1
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TAV
GPTM Timer A Value
0x50
-1
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TBPMR
GPTM TimerB Prescale Match
0x44
-1
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TBV
GPTM Timer B Value
0x54
-1
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TIMER0TAPMR
GPTM TimerA Prescale Match
0x40
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TAV
GPTM Timer A Value
0x50
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TIMER0TBPMR
GPTM TimerB Prescale Match
0x44
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TIMER0TBV
GPTM Timer B Value
0x54
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER1
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TAPMR
GPTM TimerA Prescale Match
0x40
-1
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TAV
GPTM Timer A Value
0x50
-1
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TBPMR
GPTM TimerB Prescale Match
0x44
-1
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TBV
GPTM Timer B Value
0x54
-1
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TIMER0TAPMR
GPTM TimerA Prescale Match
0x40
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TAV
GPTM Timer A Value
0x50
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TIMER0TBPMR
GPTM TimerB Prescale Match
0x44
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TIMER0TBV
GPTM Timer B Value
0x54
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER2
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TAPMR
GPTM TimerA Prescale Match
0x40
-1
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TAV
GPTM Timer A Value
0x50
-1
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TBPMR
GPTM TimerB Prescale Match
0x44
-1
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TBV
GPTM Timer B Value
0x54
-1
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TIMER0TAPMR
GPTM TimerA Prescale Match
0x40
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TAV
GPTM Timer A Value
0x50
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TIMER0TBPMR
GPTM TimerB Prescale Match
0x44
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TIMER0TBV
GPTM Timer B Value
0x54
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER3
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TAPMR
GPTM TimerA Prescale Match
0x40
-1
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TAV
GPTM Timer A Value
0x50
-1
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TBPMR
GPTM TimerB Prescale Match
0x44
-1
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TBV
GPTM Timer B Value
0x54
-1
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TAMCINT
GPTM Timer A Mode Match Interrupt Clear
4
5
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBMCINT
GPTM Timer B Mode Match Interrupt Clear
11
12
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TAMIM
GPTM Timer A Mode Match Interrupt Mask
4
5
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBMIM
GPTM Timer B Mode Match Interrupt Mask
11
12
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TAMMIS
GPTM Timer A Mode Match Masked Interrupt
4
5
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBMMIS
GPTM Timer B Mode Match Masked Interrupt
11
12
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TAMRIS
GPTM Timer A Mode Match Raw Interrupt
4
5
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBMRIS
GPTM Timer B Mode Match Raw Interrupt
11
12
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACDIR
GPTM Timer A Count Direction
4
5
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMIE
GPTM Timer A Match Interrupt Enable
5
6
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER_TAMR_TASNAPS
GPTM Timer A Snap-Shot Mode
7
8
TIMER_TAMR_TAWOT
GPTM Timer A Wait-on-Trigger
6
7
TIMER0TAPMR
GPTM TimerA Prescale Match
0x40
read-write
n
0x0
0x0
TIMER_TAPMR_TAPSMR
GPTM TimerA Prescale Match
0
8
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TAV
GPTM Timer A Value
0x50
read-write
n
0x0
0x0
TIMER_TAV_TAVH
GPTM Timer A Value High
16
32
TIMER_TAV_TAVL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCDIR
GPTM Timer B Count Direction
4
5
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMIE
GPTM Timer B Match Interrupt Enable
5
6
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER_TBMR_TBSNAPS
GPTM Timer B Snap-Shot Mode
7
8
TIMER_TBMR_TBWOT
GPTM Timer B Wait-on-Trigger
6
7
TIMER0TBPMR
GPTM TimerB Prescale Match
0x44
read-write
n
0x0
0x0
TIMER_TBPMR_TBPSMR
GPTM TimerB Prescale Match
0
8
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
24
TIMER0TBV
GPTM Timer B Value
0x54
read-write
n
0x0
0x0
TIMER_TBV_TBVL
GPTM Timer B Register
0
16
UART0
Register map for UART0 peripheral
UART
0x0
0x0
0x1000
registers
n
CTL
UART Control
0x30
-1
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
DMACTL
UART DMA Control
0x48
-1
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
UART Data
0x0
-1
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
ECR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
FBRD
UART Fractional Baud-Rate Divisor
0x28
-1
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
FR
UART Flag
0x18
-1
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
IBRD
UART Integer Baud-Rate Divisor
0x24
-1
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
ICR
UART Interrupt Clear
0x44
-1
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
IFLS
UART Interrupt FIFO Level Select
0x34
-1
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO and lt = 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO and lt = 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO and lt = 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO and lt = 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO and lt = 7/8 full
0x4
ILPR
UART IrDA Low-Power Register
0x20
-1
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
IM
UART Interrupt Mask
0x38
-1
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
LCRH
UART Line Control
0x2C
-1
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
LCTL
UART LIN Control
0x90
-1
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
LSS
UART LIN Snap Shot
0x94
-1
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
LTIM
UART LIN Timer
0x98
-1
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
MIS
UART Masked Interrupt Status
0x40
-1
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
RIS
UART Raw Interrupt Status
0x3C
-1
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
RSR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART0CTL
UART Control
0x30
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
UART0DMACTL
UART DMA Control
0x48
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
UART0DR
UART Data
0x0
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
UART0ECR
UART Receive Status/Error Clear
UART_ALT
0x4
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
UART0FBRD
UART Fractional Baud-Rate Divisor
0x28
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
UART0FR
UART Flag
0x18
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
UART0IBRD
UART Integer Baud-Rate Divisor
0x24
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
UART0ICR
UART Interrupt Clear
0x44
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
UART0IFLS
UART Interrupt FIFO Level Select
0x34
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO <= 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO <= 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO <= 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO <= 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO <= 7/8 full
0x4
UART0ILPR
UART IrDA Low-Power Register
0x20
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
UART0IM
UART Interrupt Mask
0x38
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
UART0LCRH
UART Line Control
0x2C
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
UART0LCTL
UART LIN Control
0x90
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
UART0LSS
UART LIN Snap Shot
0x94
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
UART0LTIM
UART LIN Timer
0x98
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
UART0MIS
UART Masked Interrupt Status
0x40
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
UART0RIS
UART Raw Interrupt Status
0x3C
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
UART0RSR
UART Receive Status/Error Clear
0x4
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART1
Register map for UART0 peripheral
UART
0x0
0x0
0x1000
registers
n
CTL
UART Control
0x30
-1
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
DMACTL
UART DMA Control
0x48
-1
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
UART Data
0x0
-1
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
ECR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
FBRD
UART Fractional Baud-Rate Divisor
0x28
-1
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
FR
UART Flag
0x18
-1
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
IBRD
UART Integer Baud-Rate Divisor
0x24
-1
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
ICR
UART Interrupt Clear
0x44
-1
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
IFLS
UART Interrupt FIFO Level Select
0x34
-1
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO and lt = 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO and lt = 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO and lt = 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO and lt = 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO and lt = 7/8 full
0x4
ILPR
UART IrDA Low-Power Register
0x20
-1
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
IM
UART Interrupt Mask
0x38
-1
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
LCRH
UART Line Control
0x2C
-1
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
LCTL
UART LIN Control
0x90
-1
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
LSS
UART LIN Snap Shot
0x94
-1
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
LTIM
UART LIN Timer
0x98
-1
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
MIS
UART Masked Interrupt Status
0x40
-1
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
RIS
UART Raw Interrupt Status
0x3C
-1
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
RSR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART0CTL
UART Control
0x30
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
UART0DMACTL
UART DMA Control
0x48
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
UART0DR
UART Data
0x0
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
UART0ECR
UART Receive Status/Error Clear
UART_ALT
0x4
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
UART0FBRD
UART Fractional Baud-Rate Divisor
0x28
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
UART0FR
UART Flag
0x18
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
UART0IBRD
UART Integer Baud-Rate Divisor
0x24
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
UART0ICR
UART Interrupt Clear
0x44
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
UART0IFLS
UART Interrupt FIFO Level Select
0x34
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO <= 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO <= 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO <= 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO <= 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO <= 7/8 full
0x4
UART0ILPR
UART IrDA Low-Power Register
0x20
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
UART0IM
UART Interrupt Mask
0x38
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
UART0LCRH
UART Line Control
0x2C
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
UART0LCTL
UART LIN Control
0x90
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
UART0LSS
UART LIN Snap Shot
0x94
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
UART0LTIM
UART LIN Timer
0x98
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
UART0MIS
UART Masked Interrupt Status
0x40
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
UART0RIS
UART Raw Interrupt Status
0x3C
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
UART0RSR
UART Receive Status/Error Clear
0x4
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART2
Register map for UART0 peripheral
UART
0x0
0x0
0x1000
registers
n
CTL
UART Control
0x30
-1
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
DMACTL
UART DMA Control
0x48
-1
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
UART Data
0x0
-1
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
ECR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
FBRD
UART Fractional Baud-Rate Divisor
0x28
-1
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
FR
UART Flag
0x18
-1
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
IBRD
UART Integer Baud-Rate Divisor
0x24
-1
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
ICR
UART Interrupt Clear
0x44
-1
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
IFLS
UART Interrupt FIFO Level Select
0x34
-1
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO and lt = 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO and lt = 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO and lt = 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO and lt = 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO and lt = 7/8 full
0x4
ILPR
UART IrDA Low-Power Register
0x20
-1
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
IM
UART Interrupt Mask
0x38
-1
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
LCRH
UART Line Control
0x2C
-1
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
LCTL
UART LIN Control
0x90
-1
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
LSS
UART LIN Snap Shot
0x94
-1
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
LTIM
UART LIN Timer
0x98
-1
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
MIS
UART Masked Interrupt Status
0x40
-1
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
RIS
UART Raw Interrupt Status
0x3C
-1
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
RSR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART0CTL
UART Control
0x30
read-write
n
0x0
0x0
UART_CTL_CTSEN
Enable Clear To Send
15
16
UART_CTL_DTR
Data Terminal Ready
10
11
UART_CTL_EOT
End of Transmission
4
5
UART_CTL_HSE
High-Speed Enable
5
6
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_LIN
LIN Mode Enable
6
7
UART_CTL_RTS
Request to Send
11
12
UART_CTL_RTSEN
Enable Request to Send
14
15
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_SMART
ISO 7816 Smart Card Support
3
4
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
UART0DMACTL
UART DMA Control
0x48
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
UART0DR
UART Data
0x0
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
UART0ECR
UART Receive Status/Error Clear
UART_ALT
0x4
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
UART0FBRD
UART Fractional Baud-Rate Divisor
0x28
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
UART0FR
UART Flag
0x18
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_CTS
Clear To Send
0
1
UART_FR_DCD
Data Carrier Detect
2
3
UART_FR_DSR
Data Set Ready
1
2
UART_FR_RI
Ring Indicator
8
9
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
UART0IBRD
UART Integer Baud-Rate Divisor
0x24
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
UART0ICR
UART Interrupt Clear
0x44
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_CTSMIC
UART Clear to Send Modem Interrupt Clear
1
2
write-only
UART_ICR_DCDMIC
UART Data Carrier Detect Modem Interrupt Clear
2
3
write-only
UART_ICR_DSRMIC
UART Data Set Ready Modem Interrupt Clear
3
4
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_LME1IC
LIN Mode Edge 1 Interrupt Clear
14
15
write-only
UART_ICR_LME5IC
LIN Mode Edge 5 Interrupt Clear
15
16
write-only
UART_ICR_LMSBIC
LIN Mode Sync Break Interrupt Clear
13
14
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RIMIC
UART Ring Indicator Modem Interrupt Clear
0
1
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
UART0IFLS
UART Interrupt FIFO Level Select
0x34
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO <= 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO <= 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO <= 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO <= 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO <= 7/8 full
0x4
UART0ILPR
UART IrDA Low-Power Register
0x20
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
UART0IM
UART Interrupt Mask
0x38
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_CTSMIM
UART Clear to Send Modem Interrupt Mask
1
2
UART_IM_DCDMIM
UART Data Carrier Detect Modem Interrupt Mask
2
3
UART_IM_DSRMIM
UART Data Set Ready Modem Interrupt Mask
3
4
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_LME1IM
LIN Mode Edge 1 Interrupt Mask
14
15
UART_IM_LME5IM
LIN Mode Edge 5 Interrupt Mask
15
16
UART_IM_LMSBIM
LIN Mode Sync Break Interrupt Mask
13
14
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RIMIM
UART Ring Indicator Modem Interrupt Mask
0
1
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
UART0LCRH
UART Line Control
0x2C
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
UART0LCTL
UART LIN Control
0x90
read-write
n
0x0
0x0
UART_LCTL_BLEN
Sync Break Length
4
6
UART_LCTL_BLEN_13T
Sync break length is 13T bits (default)
0x0
UART_LCTL_BLEN_14T
Sync break length is 14T bits
0x1
UART_LCTL_BLEN_15T
Sync break length is 15T bits
0x2
UART_LCTL_BLEN_16T
Sync break length is 16T bits
0x3
UART_LCTL_MASTER
LIN Master Enable
0
1
UART0LSS
UART LIN Snap Shot
0x94
read-write
n
0x0
0x0
UART_LSS_TSS
Timer Snap Shot
0
16
UART0LTIM
UART LIN Timer
0x98
read-write
n
0x0
0x0
UART_LTIM_TIMER
Timer Value
0
16
UART0MIS
UART Masked Interrupt Status
0x40
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_CTSMIS
UART Clear to Send Modem Masked Interrupt Status
1
2
UART_MIS_DCDMIS
UART Data Carrier Detect Modem Masked Interrupt Status
2
3
UART_MIS_DSRMIS
UART Data Set Ready Modem Masked Interrupt Status
3
4
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_LME1MIS
LIN Mode Edge 1 Masked Interrupt Status
14
15
UART_MIS_LME5MIS
LIN Mode Edge 5 Masked Interrupt Status
15
16
UART_MIS_LMSBMIS
LIN Mode Sync Break Masked Interrupt Status
13
14
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RIMIS
UART Ring Indicator Modem Masked Interrupt Status
0
1
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
UART0RIS
UART Raw Interrupt Status
0x3C
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_CTSRIS
UART Clear to Send Modem Raw Interrupt Status
1
2
UART_RIS_DCDRIS
UART Data Carrier Detect Modem Raw Interrupt Status
2
3
UART_RIS_DSRRIS
UART Data Set Ready Modem Raw Interrupt Status
3
4
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_LME1RIS
LIN Mode Edge 1 Raw Interrupt Status
14
15
UART_RIS_LME5RIS
LIN Mode Edge 5 Raw Interrupt Status
15
16
UART_RIS_LMSBRIS
LIN Mode Sync Break Raw Interrupt Status
13
14
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RIRIS
UART Ring Indicator Modem Raw Interrupt Status
0
1
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
UART0RSR
UART Receive Status/Error Clear
0x4
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UDMA
Register map for UDMA peripheral
UDM
0x0
0x0
0x1000
registers
n
ALTBASE
DMA Alternate Channel Control Base Pointer
0xC
-1
read-write
n
0x0
0x0
UDMA_ALTBASE_ADDR
Alternate Channel Address Pointer
0
32
ALTCLR
DMA Channel Primary Alternate Clear
0x34
-1
write-only
n
0x0
0x0
UDMA_ALTCLR_CLR
Channel [n] Alternate Clear
0
32
write-only
ALTSET
DMA Channel Primary Alternate Set
0x30
-1
read-write
n
0x0
0x0
UDMA_ALTSET_SET
Channel [n] Alternate Set
0
32
CFG
DMA Configuration
0x4
-1
write-only
n
0x0
0x0
UDMA_CFG_MASTEN
Controller Master Enable
0
1
write-only
CHASGN
DMA Channel Assignment
0x500
-1
read-write
n
0x0
0x0
UDMA_CHASGN
Channel [n] Assignment Select
0
32
UDMA_CHASGN_PRIMARY
Use the primary channel assignment
0x0
UDMA_CHASGN_SECONDARY
Use the secondary channel assignment
0x1
CTLBASE
DMA Channel Control Base Pointer
0x8
-1
read-write
n
0x0
0x0
UDMA_CTLBASE_ADDR
Channel Control Base Address
10
32
ENACLR
DMA Channel Enable Clear
0x2C
-1
write-only
n
0x0
0x0
UDMA_ENACLR_CLR
Clear Channel [n] Enable Clear
0
32
write-only
ENASET
DMA Channel Enable Set
0x28
-1
read-write
n
0x0
0x0
UDMA_ENASET_SET
Channel [n] Enable Set
0
32
ERRCLR
DMA Bus Error Clear
0x4C
-1
read-write
n
0x0
0x0
UDMA_ERRCLR_ERRCLR
uDMA Bus Error Status
0
1
PRIOCLR
DMA Channel Priority Clear
0x3C
-1
write-only
n
0x0
0x0
UDMA_PRIOCLR_CLR
Channel [n] Priority Clear
0
32
write-only
PRIOSET
DMA Channel Priority Set
0x38
-1
read-write
n
0x0
0x0
UDMA_PRIOSET_SET
Channel [n] Priority Set
0
32
REQMASKCLR
DMA Channel Request Mask Clear
0x24
-1
write-only
n
0x0
0x0
UDMA_REQMASKCLR_CLR
Channel [n] Request Mask Clear
0
32
write-only
REQMASKSET
DMA Channel Request Mask Set
0x20
-1
read-write
n
0x0
0x0
UDMA_REQMASKSET_SET
Channel [n] Request Mask Set
0
32
STAT
DMA Status
0x0
-1
read-write
n
0x0
0x0
UDMA_STAT_DMACHANS
Available uDMA Channels Minus 1
16
21
UDMA_STAT_MASTEN
Master Enable Status
0
1
UDMA_STAT_STATE
Control State Machine Status
4
8
UDMA_STAT_STATE_IDLE
Idle
0x0
UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x1
UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x2
UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x3
UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x4
UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x5
UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x6
UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x7
UDMA_STAT_STATE_STALL
Stalled
0x8
UDMA_STAT_STATE_DONE
Done
0x9
UDMA_STAT_STATE_UNDEF
Undefined
0xa
SWREQ
DMA Channel Software Request
0x14
-1
write-only
n
0x0
0x0
UDMA_SWREQ
Channel [n] Software Request
0
32
write-only
UDMAALTBASE
DMA Alternate Channel Control Base Pointer
0xC
read-write
n
0x0
0x0
UDMA_ALTBASE_ADDR
Alternate Channel Address Pointer
0
32
UDMAALTCLR
DMA Channel Primary Alternate Clear
0x34
write-only
n
0x0
0x0
UDMA_ALTCLR_CLR
Channel [n] Alternate Clear
0
32
write-only
UDMAALTSET
DMA Channel Primary Alternate Set
0x30
read-write
n
0x0
0x0
UDMA_ALTSET_SET
Channel [n] Alternate Set
0
32
UDMACFG
DMA Configuration
0x4
write-only
n
0x0
0x0
UDMA_CFG_MASTEN
Controller Master Enable
0
1
write-only
UDMACHASGN
DMA Channel Assignment
0x500
read-write
n
0x0
0x0
UDMA_CHASGN
Channel [n] Assignment Select
0
32
UDMA_CHASGN_PRIMARY
Use the primary channel assignment
0x0
UDMA_CHASGN_SECONDARY
Use the secondary channel assignment
0x1
UDMACTLBASE
DMA Channel Control Base Pointer
0x8
read-write
n
0x0
0x0
UDMA_CTLBASE_ADDR
Channel Control Base Address
10
32
UDMAENACLR
DMA Channel Enable Clear
0x2C
write-only
n
0x0
0x0
UDMA_ENACLR_CLR
Clear Channel [n] Enable Clear
0
32
write-only
UDMAENASET
DMA Channel Enable Set
0x28
read-write
n
0x0
0x0
UDMA_ENASET_SET
Channel [n] Enable Set
0
32
UDMAERRCLR
DMA Bus Error Clear
0x4C
read-write
n
0x0
0x0
UDMA_ERRCLR_ERRCLR
uDMA Bus Error Status
0
1
UDMAPRIOCLR
DMA Channel Priority Clear
0x3C
write-only
n
0x0
0x0
UDMA_PRIOCLR_CLR
Channel [n] Priority Clear
0
32
write-only
UDMAPRIOSET
DMA Channel Priority Set
0x38
read-write
n
0x0
0x0
UDMA_PRIOSET_SET
Channel [n] Priority Set
0
32
UDMAREQMASKCLR
DMA Channel Request Mask Clear
0x24
write-only
n
0x0
0x0
UDMA_REQMASKCLR_CLR
Channel [n] Request Mask Clear
0
32
write-only
UDMAREQMASKSET
DMA Channel Request Mask Set
0x20
read-write
n
0x0
0x0
UDMA_REQMASKSET_SET
Channel [n] Request Mask Set
0
32
UDMASTAT
DMA Status
0x0
read-write
n
0x0
0x0
UDMA_STAT_DMACHANS
Available uDMA Channels Minus 1
16
21
UDMA_STAT_MASTEN
Master Enable Status
0
1
UDMA_STAT_STATE
Control State Machine Status
4
8
UDMA_STAT_STATE_IDLE
Idle
0x0
UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x1
UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x2
UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x3
UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x4
UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x5
UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x6
UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x7
UDMA_STAT_STATE_STALL
Stalled
0x8
UDMA_STAT_STATE_DONE
Done
0x9
UDMA_STAT_STATE_UNDEF
Undefined
0xa
UDMASWREQ
DMA Channel Software Request
0x14
write-only
n
0x0
0x0
UDMA_SWREQ
Channel [n] Software Request
0
32
write-only
UDMAUSEBURSTCLR
DMA Channel Useburst Clear
0x1C
write-only
n
0x0
0x0
UDMA_USEBURSTCLR_CLR
Channel [n] Useburst Clear
0
32
write-only
UDMAUSEBURSTSET
DMA Channel Useburst Set
0x18
read-write
n
0x0
0x0
UDMA_USEBURSTSET_SET
Channel [n] Useburst Set
0
32
UDMAWAITSTAT
DMA Channel Wait-on-Request Status
0x10
read-write
n
0x0
0x0
UDMA_WAITSTAT_WAITREQ
Channel [n] Wait Status
0
32
USEBURSTCLR
DMA Channel Useburst Clear
0x1C
-1
write-only
n
0x0
0x0
UDMA_USEBURSTCLR_CLR
Channel [n] Useburst Clear
0
32
write-only
USEBURSTSET
DMA Channel Useburst Set
0x18
-1
read-write
n
0x0
0x0
UDMA_USEBURSTSET_SET
Channel [n] Useburst Set
0
32
WAITSTAT
DMA Channel Wait-on-Request Status
0x10
-1
read-write
n
0x0
0x0
UDMA_WAITSTAT_WAITREQ
Channel [n] Wait Status
0
32
USB0
Register map for USB0 peripheral
USB
0x0
0x0
0x1000
registers
n
CONTIM
USB Connect Timing
0x7A
8
read-write
n
0x0
0x0
USB_CONTIM_WTCON
Connect Wait
4
8
USB_CONTIM_WTID
Wait ID
0
4
COUNT0
USB Receive Byte Count Endpoint 0
0x108
8
read-write
n
0x0
0x0
USB_COUNT0_COUNT
FIFO Count
0
7
CSRH0
USB Control and Status Endpoint 0 High
0x103
8
write-only
n
0x0
0x0
USB_CSRH0_DT
Data Toggle
1
2
write-only
USB_CSRH0_DTWE
Data Toggle Write Enable
2
3
write-only
USB_CSRH0_FLUSH
Flush FIFO
0
1
write-only
CSRL0
USB Control and Status Endpoint 0 Low
0x102
8
write-only
n
0x0
0x0
USB_CSRL0_DATAEND
Data End
3
4
write-only
USB_CSRL0_ERROR
Error
4
5
write-only
USB_CSRL0_NAKTO
NAK Timeout
7
8
write-only
USB_CSRL0_REQPKT
Request Packet
5
6
write-only
USB_CSRL0_RXRDY
Receive Packet Ready
0
1
write-only
USB_CSRL0_RXRDYC
RXRDY Clear
6
7
write-only
USB_CSRL0_SETEND
Setup End
4
5
write-only
USB_CSRL0_SETENDC
Setup End Clear
7
8
write-only
USB_CSRL0_SETUP
Setup Packet
3
4
write-only
USB_CSRL0_STALL
Send Stall
5
6
write-only
USB_CSRL0_STALLED
Endpoint Stalled
2
3
write-only
USB_CSRL0_STATUS
STATUS Packet
6
7
write-only
USB_CSRL0_TXRDY
Transmit Packet Ready
1
2
write-only
DEVCTL
USB Device Control
0x60
8
read-write
n
0x0
0x0
USB_DEVCTL_DEV
Device Mode
7
8
USB_DEVCTL_FSDEV
Full-Speed Device Detected
6
7
USB_DEVCTL_HOST
Host Mode
2
3
USB_DEVCTL_HOSTREQ
Host Request
1
2
USB_DEVCTL_LSDEV
Low-Speed Device Detected
5
6
USB_DEVCTL_SESSION
Session Start/End
0
1
USB_DEVCTL_VBUS
VBUS Level
3
5
USB_DEVCTL_VBUS_NONE
Below SessionEnd
0x0
USB_DEVCTL_VBUS_SEND
Above SessionEnd, below AValid
0x1
USB_DEVCTL_VBUS_AVALID
Above AValid, below VBUSValid
0x2
USB_DEVCTL_VBUS_VALID
Above VBUSValid
0x3
DMASEL
USB DMA Select
0x450
-1
read-write
n
0x0
0x0
USB_DMASEL_DMAARX
DMA A RX Select
0
4
USB_DMASEL_DMAATX
DMA A TX Select
4
8
USB_DMASEL_DMABRX
DMA B RX Select
8
12
USB_DMASEL_DMABTX
DMA B TX Select
12
16
USB_DMASEL_DMACRX
DMA C RX Select
16
20
USB_DMASEL_DMACTX
DMA C TX Select
20
24
DRIM
USB Device RESUME Interrupt Mask
0x414
-1
read-write
n
0x0
0x0
USB_DRIM_RESUME
RESUME Interrupt Mask
0
1
DRISC
USB Device RESUME Interrupt Status and Clear
0x418
-1
write-only
n
0x0
0x0
USB_DRISC_RESUME
RESUME Interrupt Status and Clear
0
1
write-only
DRRIS
USB Device RESUME Raw Interrupt Status
0x410
-1
read-write
n
0x0
0x0
USB_DRRIS_RESUME
RESUME Interrupt Status
0
1
EPC
USB External Power Control
0x400
-1
read-write
n
0x0
0x0
USB_EPC_EPEN
External Power Supply Enable Configuration
0
2
USB_EPC_EPEN_LOW
Power Enable Active Low
0x0
USB_EPC_EPEN_HIGH
Power Enable Active High
0x1
USB_EPC_EPEN_VBLOW
Power Enable High if VBUS Low
0x2
USB_EPC_EPEN_VBHIGH
Power Enable High if VBUS High
0x3
USB_EPC_EPENDE
EPEN Drive Enable
2
3
USB_EPC_PFLTACT
Power Fault Action
8
10
USB_EPC_PFLTACT_UNCHG
Unchanged
0x0
USB_EPC_PFLTACT_TRIS
Tristate
0x1
USB_EPC_PFLTACT_LOW
Low
0x2
USB_EPC_PFLTACT_HIGH
High
0x3
USB_EPC_PFLTAEN
Power Fault Action Enable
6
7
USB_EPC_PFLTEN
Power Fault Input Enable
4
5
USB_EPC_PFLTSEN_HIGH
Power Fault Sense
5
6
EPCIM
USB External Power Control Interrupt Mask
0x408
-1
read-write
n
0x0
0x0
USB_EPCIM_PF
USB Power Fault Interrupt Mask
0
1
EPCISC
USB External Power Control Interrupt Status and Clear
0x40C
-1
read-write
n
0x0
0x0
USB_EPCISC_PF
USB Power Fault Interrupt Status and Clear
0
1
EPCRIS
USB External Power Control Raw Interrupt Status
0x404
-1
read-write
n
0x0
0x0
USB_EPCRIS_PF
USB Power Fault Interrupt Status
0
1
EPIDX
USB Endpoint Index
0xE
8
read-write
n
0x0
0x0
USB_EPIDX_EPIDX
Endpoint Index
0
4
FADDR
USB Device Functional Address
0x0
8
read-write
n
0x0
0x0
USB_FADDR
Function Address
0
7
FIFO0
USB FIFO Endpoint 0
0x20
-1
read-write
n
0x0
0x0
USB_FIFO0_EPDATA
Endpoint Data
0
32
FIFO1
USB FIFO Endpoint 1
0x24
-1
read-write
n
0x0
0x0
USB_FIFO1_EPDATA
Endpoint Data
0
32
FIFO10
USB FIFO Endpoint 10
0x48
-1
read-write
n
0x0
0x0
USB_FIFO10_EPDATA
Endpoint Data
0
32
FIFO11
USB FIFO Endpoint 11
0x4C
-1
read-write
n
0x0
0x0
USB_FIFO11_EPDATA
Endpoint Data
0
32
FIFO12
USB FIFO Endpoint 12
0x50
-1
read-write
n
0x0
0x0
USB_FIFO12_EPDATA
Endpoint Data
0
32
FIFO13
USB FIFO Endpoint 13
0x54
-1
read-write
n
0x0
0x0
USB_FIFO13_EPDATA
Endpoint Data
0
32
FIFO14
USB FIFO Endpoint 14
0x58
-1
read-write
n
0x0
0x0
USB_FIFO14_EPDATA
Endpoint Data
0
32
FIFO15
USB FIFO Endpoint 15
0x5C
-1
read-write
n
0x0
0x0
USB_FIFO15_EPDATA
Endpoint Data
0
32
FIFO2
USB FIFO Endpoint 2
0x28
-1
read-write
n
0x0
0x0
USB_FIFO2_EPDATA
Endpoint Data
0
32
FIFO3
USB FIFO Endpoint 3
0x2C
-1
read-write
n
0x0
0x0
USB_FIFO3_EPDATA
Endpoint Data
0
32
FIFO4
USB FIFO Endpoint 4
0x30
-1
read-write
n
0x0
0x0
USB_FIFO4_EPDATA
Endpoint Data
0
32
FIFO5
USB FIFO Endpoint 5
0x34
-1
read-write
n
0x0
0x0
USB_FIFO5_EPDATA
Endpoint Data
0
32
FIFO6
USB FIFO Endpoint 6
0x38
-1
read-write
n
0x0
0x0
USB_FIFO6_EPDATA
Endpoint Data
0
32
FIFO7
USB FIFO Endpoint 7
0x3C
-1
read-write
n
0x0
0x0
USB_FIFO7_EPDATA
Endpoint Data
0
32
FIFO8
USB FIFO Endpoint 8
0x40
-1
read-write
n
0x0
0x0
USB_FIFO8_EPDATA
Endpoint Data
0
32
FIFO9
USB FIFO Endpoint 9
0x44
-1
read-write
n
0x0
0x0
USB_FIFO9_EPDATA
Endpoint Data
0
32
FRAME
USB Frame Value
0xC
16
read-write
n
0x0
0x0
USB_FRAME
Frame Number
0
11
FSEOF
USB Full-Speed Last Transaction to End of Frame Timing
0x7D
8
read-write
n
0x0
0x0
USB_FSEOF_FSEOFG
Full-Speed End-of-Frame Gap
0
8
GPCS
USB General-Purpose Control and Status
0x41C
-1
read-write
n
0x0
0x0
USB_GPCS_DEVMOD
Device Mode
0
1
USB_GPCS_DEVMODOTG
Enable Device Mode
1
2
IDVIM
USB ID Valid Detect Interrupt Mask
0x448
-1
read-write
n
0x0
0x0
USB_IDVIM_ID
ID Valid Detect Interrupt Mask
0
1
IDVISC
USB ID Valid Detect Interrupt Status and Clear
0x44C
-1
read-write
n
0x0
0x0
USB_IDVISC_ID
ID Valid Detect Interrupt Status and Clear
0
1
IDVRIS
USB ID Valid Detect Raw Interrupt Status
0x444
-1
read-write
n
0x0
0x0
USB_IDVRIS_ID
ID Valid Detect Raw Interrupt Status
0
1
IE
USB Interrupt Enable
0xB
8
read-write
n
0x0
0x0
USB_IE_BABBLE
Enable Babble Interrupt
2
3
USB_IE_CONN
Enable Connect Interrupt
4
5
USB_IE_DISCON
Enable Disconnect Interrupt
5
6
USB_IE_RESET
Enable RESET Interrupt
2
3
USB_IE_RESUME
Enable RESUME Interrupt
1
2
USB_IE_SESREQ
Enable Session Request
6
7
USB_IE_SOF
Enable Start-of-Frame Interrupt
3
4
USB_IE_SUSPND
Enable SUSPEND Interrupt
0
1
USB_IE_VBUSERR
Enable VBUS Error Interrupt
7
8
IS
USB General Interrupt Status
0xA
8
read-write
n
0x0
0x0
USB_IS_BABBLE
Babble Detected
2
3
USB_IS_CONN
Session Connect
4
5
USB_IS_DISCON
Session Disconnect
5
6
USB_IS_RESET
RESET Signaling Detected
2
3
USB_IS_RESUME
RESUME Signaling Detected
1
2
USB_IS_SESREQ
SESSION REQUEST
6
7
USB_IS_SOF
Start of Frame
3
4
USB_IS_SUSPEND
SUSPEND Signaling Detected
0
1
USB_IS_VBUSERR
VBUS Error
7
8
LSEOF
USB Low-Speed Last Transaction to End of Frame Timing
0x7E
8
read-write
n
0x0
0x0
USB_LSEOF_LSEOFG
Low-Speed End-of-Frame Gap
0
8
NAKLMT
USB NAK Limit
0x10B
8
read-write
n
0x0
0x0
USB_NAKLMT_NAKLMT
EP0 NAK Limit
0
5
POWER
USB Power
0x1
8
read-write
n
0x0
0x0
USB_POWER_ISOUP
Isochronous Update
7
8
USB_POWER_PWRDNPHY
Power Down PHY
0
1
USB_POWER_RESET
RESET Signaling
3
4
USB_POWER_RESUME
RESUME Signaling
2
3
USB_POWER_SOFTCONN
Soft Connect/Disconnect
6
7
USB_POWER_SUSPEND
SUSPEND Mode
1
2
RQPKTCOUNT1
USB Request Packet Count in Block Transfer Endpoint 1
0x304
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT1
Block Transfer Packet Count
0
16
RQPKTCOUNT10
USB Request Packet Count in Block Transfer Endpoint 10
0x328
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT10_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT11
USB Request Packet Count in Block Transfer Endpoint 11
0x32C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT11_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT12
USB Request Packet Count in Block Transfer Endpoint 12
0x330
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT12_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT13
USB Request Packet Count in Block Transfer Endpoint 13
0x334
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT13_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT14
USB Request Packet Count in Block Transfer Endpoint 14
0x338
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT14_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT15
USB Request Packet Count in Block Transfer Endpoint 15
0x33C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT15_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT2
USB Request Packet Count in Block Transfer Endpoint 2
0x308
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT2
Block Transfer Packet Count
0
16
RQPKTCOUNT3
USB Request Packet Count in Block Transfer Endpoint 3
0x30C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT3
Block Transfer Packet Count
0
16
RQPKTCOUNT4
USB Request Packet Count in Block Transfer Endpoint 4
0x310
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT4_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT5
USB Request Packet Count in Block Transfer Endpoint 5
0x314
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT5_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT6
USB Request Packet Count in Block Transfer Endpoint 6
0x318
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT6_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT7
USB Request Packet Count in Block Transfer Endpoint 7
0x31C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT7_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT8
USB Request Packet Count in Block Transfer Endpoint 8
0x320
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT8_COUNT
Block Transfer Packet Count
0
16
RQPKTCOUNT9
USB Request Packet Count in Block Transfer Endpoint 9
0x324
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT9_COUNT
Block Transfer Packet Count
0
16
RXCOUNT1
USB Receive Byte Count Endpoint 1
0x118
16
read-write
n
0x0
0x0
USB_RXCOUNT1_COUNT
Receive Packet Count
0
13
RXCOUNT10
USB Receive Byte Count Endpoint 10
0x1A8
16
read-write
n
0x0
0x0
USB_RXCOUNT10_COUNT
Receive Packet Count
0
13
RXCOUNT11
USB Receive Byte Count Endpoint 11
0x1B8
16
read-write
n
0x0
0x0
USB_RXCOUNT11_COUNT
Receive Packet Count
0
13
RXCOUNT12
USB Receive Byte Count Endpoint 12
0x1C8
16
read-write
n
0x0
0x0
USB_RXCOUNT12_COUNT
Receive Packet Count
0
13
RXCOUNT13
USB Receive Byte Count Endpoint 13
0x1D8
16
read-write
n
0x0
0x0
USB_RXCOUNT13_COUNT
Receive Packet Count
0
13
RXCOUNT14
USB Receive Byte Count Endpoint 14
0x1E8
16
read-write
n
0x0
0x0
USB_RXCOUNT14_COUNT
Receive Packet Count
0
13
RXCOUNT15
USB Receive Byte Count Endpoint 15
0x1F8
16
read-write
n
0x0
0x0
USB_RXCOUNT15_COUNT
Receive Packet Count
0
13
RXCOUNT2
USB Receive Byte Count Endpoint 2
0x128
16
read-write
n
0x0
0x0
USB_RXCOUNT2_COUNT
Receive Packet Count
0
13
RXCOUNT3
USB Receive Byte Count Endpoint 3
0x138
16
read-write
n
0x0
0x0
USB_RXCOUNT3_COUNT
Receive Packet Count
0
13
RXCOUNT4
USB Receive Byte Count Endpoint 4
0x148
16
read-write
n
0x0
0x0
USB_RXCOUNT4_COUNT
Receive Packet Count
0
13
RXCOUNT5
USB Receive Byte Count Endpoint 5
0x158
16
read-write
n
0x0
0x0
USB_RXCOUNT5_COUNT
Receive Packet Count
0
13
RXCOUNT6
USB Receive Byte Count Endpoint 6
0x168
16
read-write
n
0x0
0x0
USB_RXCOUNT6_COUNT
Receive Packet Count
0
13
RXCOUNT7
USB Receive Byte Count Endpoint 7
0x178
16
read-write
n
0x0
0x0
USB_RXCOUNT7_COUNT
Receive Packet Count
0
13
RXCOUNT8
USB Receive Byte Count Endpoint 8
0x188
16
read-write
n
0x0
0x0
USB_RXCOUNT8_COUNT
Receive Packet Count
0
13
RXCOUNT9
USB Receive Byte Count Endpoint 9
0x198
16
read-write
n
0x0
0x0
USB_RXCOUNT9_COUNT
Receive Packet Count
0
13
RXCSRH1
USB Receive Control and Status Endpoint 1 High
0x117
8
read-write
n
0x0
0x0
USB_RXCSRH1_AUTOCL
Auto Clear
7
8
USB_RXCSRH1_AUTORQ
Auto Request
6
7
USB_RXCSRH1_DISNYET
Disable NYET
4
5
USB_RXCSRH1_DMAEN
DMA Request Enable
5
6
USB_RXCSRH1_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH1_DT
Data Toggle
1
2
USB_RXCSRH1_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH1_ISO
Isochronous Transfers
6
7
USB_RXCSRH1_PIDERR
PID Error
4
5
RXCSRH10
USB Receive Control and Status Endpoint 10 High
0x1A7
8
read-write
n
0x0
0x0
USB_RXCSRH10_AUTOCL
Auto Clear
7
8
USB_RXCSRH10_AUTORQ
Auto Request
6
7
USB_RXCSRH10_DISNYET
Disable NYET
4
5
USB_RXCSRH10_DMAEN
DMA Request Enable
5
6
USB_RXCSRH10_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH10_DT
Data Toggle
1
2
USB_RXCSRH10_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH10_ISO
Isochronous Transfers
6
7
USB_RXCSRH10_PIDERR
PID Error
4
5
RXCSRH11
USB Receive Control and Status Endpoint 11 High
0x1B7
8
read-write
n
0x0
0x0
USB_RXCSRH11_AUTOCL
Auto Clear
7
8
USB_RXCSRH11_AUTORQ
Auto Request
6
7
USB_RXCSRH11_DISNYET
Disable NYET
4
5
USB_RXCSRH11_DMAEN
DMA Request Enable
5
6
USB_RXCSRH11_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH11_DT
Data Toggle
1
2
USB_RXCSRH11_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH11_ISO
Isochronous Transfers
6
7
USB_RXCSRH11_PIDERR
PID Error
4
5
RXCSRH12
USB Receive Control and Status Endpoint 12 High
0x1C7
8
read-write
n
0x0
0x0
USB_RXCSRH12_AUTOCL
Auto Clear
7
8
USB_RXCSRH12_AUTORQ
Auto Request
6
7
USB_RXCSRH12_DISNYET
Disable NYET
4
5
USB_RXCSRH12_DMAEN
DMA Request Enable
5
6
USB_RXCSRH12_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH12_DT
Data Toggle
1
2
USB_RXCSRH12_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH12_ISO
Isochronous Transfers
6
7
USB_RXCSRH12_PIDERR
PID Error
4
5
RXCSRH13
USB Receive Control and Status Endpoint 13 High
0x1D7
8
read-write
n
0x0
0x0
USB_RXCSRH13_AUTOCL
Auto Clear
7
8
USB_RXCSRH13_AUTORQ
Auto Request
6
7
USB_RXCSRH13_DISNYET
Disable NYET
4
5
USB_RXCSRH13_DMAEN
DMA Request Enable
5
6
USB_RXCSRH13_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH13_DT
Data Toggle
1
2
USB_RXCSRH13_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH13_ISO
Isochronous Transfers
6
7
USB_RXCSRH13_PIDERR
PID Error
4
5
RXCSRH14
USB Receive Control and Status Endpoint 14 High
0x1E7
8
read-write
n
0x0
0x0
USB_RXCSRH14_AUTOCL
Auto Clear
7
8
USB_RXCSRH14_AUTORQ
Auto Request
6
7
USB_RXCSRH14_DISNYET
Disable NYET
4
5
USB_RXCSRH14_DMAEN
DMA Request Enable
5
6
USB_RXCSRH14_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH14_DT
Data Toggle
1
2
USB_RXCSRH14_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH14_ISO
Isochronous Transfers
6
7
USB_RXCSRH14_PIDERR
PID Error
4
5
RXCSRH15
USB Receive Control and Status Endpoint 15 High
0x1F7
8
read-write
n
0x0
0x0
USB_RXCSRH15_AUTOCL
Auto Clear
7
8
USB_RXCSRH15_AUTORQ
Auto Request
6
7
USB_RXCSRH15_DISNYET
Disable NYET
4
5
USB_RXCSRH15_DMAEN
DMA Request Enable
5
6
USB_RXCSRH15_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH15_DT
Data Toggle
1
2
USB_RXCSRH15_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH15_ISO
Isochronous Transfers
6
7
USB_RXCSRH15_PIDERR
PID Error
4
5
RXCSRH2
USB Receive Control and Status Endpoint 2 High
0x127
8
read-write
n
0x0
0x0
USB_RXCSRH2_AUTOCL
Auto Clear
7
8
USB_RXCSRH2_AUTORQ
Auto Request
6
7
USB_RXCSRH2_DISNYET
Disable NYET
4
5
USB_RXCSRH2_DMAEN
DMA Request Enable
5
6
USB_RXCSRH2_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH2_DT
Data Toggle
1
2
USB_RXCSRH2_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH2_ISO
Isochronous Transfers
6
7
USB_RXCSRH2_PIDERR
PID Error
4
5
RXCSRH3
USB Receive Control and Status Endpoint 3 High
0x137
8
read-write
n
0x0
0x0
USB_RXCSRH3_AUTOCL
Auto Clear
7
8
USB_RXCSRH3_AUTORQ
Auto Request
6
7
USB_RXCSRH3_DISNYET
Disable NYET
4
5
USB_RXCSRH3_DMAEN
DMA Request Enable
5
6
USB_RXCSRH3_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH3_DT
Data Toggle
1
2
USB_RXCSRH3_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH3_ISO
Isochronous Transfers
6
7
USB_RXCSRH3_PIDERR
PID Error
4
5
RXCSRH4
USB Receive Control and Status Endpoint 4 High
0x147
8
read-write
n
0x0
0x0
USB_RXCSRH4_AUTOCL
Auto Clear
7
8
USB_RXCSRH4_AUTORQ
Auto Request
6
7
USB_RXCSRH4_DISNYET
Disable NYET
4
5
USB_RXCSRH4_DMAEN
DMA Request Enable
5
6
USB_RXCSRH4_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH4_DT
Data Toggle
1
2
USB_RXCSRH4_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH4_ISO
Isochronous Transfers
6
7
USB_RXCSRH4_PIDERR
PID Error
4
5
RXCSRH5
USB Receive Control and Status Endpoint 5 High
0x157
8
read-write
n
0x0
0x0
USB_RXCSRH5_AUTOCL
Auto Clear
7
8
USB_RXCSRH5_AUTORQ
Auto Request
6
7
USB_RXCSRH5_DISNYET
Disable NYET
4
5
USB_RXCSRH5_DMAEN
DMA Request Enable
5
6
USB_RXCSRH5_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH5_DT
Data Toggle
1
2
USB_RXCSRH5_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH5_ISO
Isochronous Transfers
6
7
USB_RXCSRH5_PIDERR
PID Error
4
5
RXCSRH6
USB Receive Control and Status Endpoint 6 High
0x167
8
read-write
n
0x0
0x0
USB_RXCSRH6_AUTOCL
Auto Clear
7
8
USB_RXCSRH6_AUTORQ
Auto Request
6
7
USB_RXCSRH6_DISNYET
Disable NYET
4
5
USB_RXCSRH6_DMAEN
DMA Request Enable
5
6
USB_RXCSRH6_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH6_DT
Data Toggle
1
2
USB_RXCSRH6_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH6_ISO
Isochronous Transfers
6
7
USB_RXCSRH6_PIDERR
PID Error
4
5
RXCSRH7
USB Receive Control and Status Endpoint 7 High
0x177
8
read-write
n
0x0
0x0
USB_RXCSRH7_AUTOCL
Auto Clear
7
8
USB_RXCSRH7_AUTORQ
Auto Request
6
7
USB_RXCSRH7_DISNYET
Disable NYET
4
5
USB_RXCSRH7_DMAEN
DMA Request Enable
5
6
USB_RXCSRH7_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH7_DT
Data Toggle
1
2
USB_RXCSRH7_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH7_ISO
Isochronous Transfers
6
7
USB_RXCSRH7_PIDERR
PID Error
4
5
RXCSRH8
USB Receive Control and Status Endpoint 8 High
0x187
8
read-write
n
0x0
0x0
USB_RXCSRH8_AUTOCL
Auto Clear
7
8
USB_RXCSRH8_AUTORQ
Auto Request
6
7
USB_RXCSRH8_DISNYET
Disable NYET
4
5
USB_RXCSRH8_DMAEN
DMA Request Enable
5
6
USB_RXCSRH8_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH8_DT
Data Toggle
1
2
USB_RXCSRH8_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH8_ISO
Isochronous Transfers
6
7
USB_RXCSRH8_PIDERR
PID Error
4
5
RXCSRH9
USB Receive Control and Status Endpoint 9 High
0x197
8
read-write
n
0x0
0x0
USB_RXCSRH9_AUTOCL
Auto Clear
7
8
USB_RXCSRH9_AUTORQ
Auto Request
6
7
USB_RXCSRH9_DISNYET
Disable NYET
4
5
USB_RXCSRH9_DMAEN
DMA Request Enable
5
6
USB_RXCSRH9_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH9_DT
Data Toggle
1
2
USB_RXCSRH9_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH9_ISO
Isochronous Transfers
6
7
USB_RXCSRH9_PIDERR
PID Error
4
5
RXCSRL1
USB Receive Control and Status Endpoint 1 Low
0x116
8
read-write
n
0x0
0x0
USB_RXCSRL1_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL1_DATAERR
Data Error
3
4
USB_RXCSRL1_ERROR
Error
2
3
USB_RXCSRL1_FLUSH
Flush FIFO
4
5
USB_RXCSRL1_FULL
FIFO Full
1
2
USB_RXCSRL1_NAKTO
NAK Timeout
3
4
USB_RXCSRL1_OVER
Overrun
2
3
USB_RXCSRL1_REQPKT
Request Packet
5
6
USB_RXCSRL1_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL1_STALL
Send STALL
5
6
USB_RXCSRL1_STALLED
Endpoint Stalled
6
7
RXCSRL10
USB Receive Control and Status Endpoint 10 Low
0x1A6
8
read-write
n
0x0
0x0
USB_RXCSRL10_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL10_DATAERR
Data Error
3
4
USB_RXCSRL10_ERROR
Error
2
3
USB_RXCSRL10_FLUSH
Flush FIFO
4
5
USB_RXCSRL10_FULL
FIFO Full
1
2
USB_RXCSRL10_NAKTO
NAK Timeout
3
4
USB_RXCSRL10_OVER
Overrun
2
3
USB_RXCSRL10_REQPKT
Request Packet
5
6
USB_RXCSRL10_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL10_STALL
Send STALL
5
6
USB_RXCSRL10_STALLED
Endpoint Stalled
6
7
RXCSRL11
USB Receive Control and Status Endpoint 11 Low
0x1B6
8
read-write
n
0x0
0x0
USB_RXCSRL11_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL11_DATAERR
Data Error
3
4
USB_RXCSRL11_ERROR
Error
2
3
USB_RXCSRL11_FLUSH
Flush FIFO
4
5
USB_RXCSRL11_FULL
FIFO Full
1
2
USB_RXCSRL11_NAKTO
NAK Timeout
3
4
USB_RXCSRL11_OVER
Overrun
2
3
USB_RXCSRL11_REQPKT
Request Packet
5
6
USB_RXCSRL11_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL11_STALL
Send STALL
5
6
USB_RXCSRL11_STALLED
Endpoint Stalled
6
7
RXCSRL12
USB Receive Control and Status Endpoint 12 Low
0x1C6
8
read-write
n
0x0
0x0
USB_RXCSRL12_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL12_DATAERR
Data Error
3
4
USB_RXCSRL12_ERROR
Error
2
3
USB_RXCSRL12_FLUSH
Flush FIFO
4
5
USB_RXCSRL12_FULL
FIFO Full
1
2
USB_RXCSRL12_NAKTO
NAK Timeout
3
4
USB_RXCSRL12_OVER
Overrun
2
3
USB_RXCSRL12_REQPKT
Request Packet
5
6
USB_RXCSRL12_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL12_STALL
Send STALL
5
6
USB_RXCSRL12_STALLED
Endpoint Stalled
6
7
RXCSRL13
USB Receive Control and Status Endpoint 13 Low
0x1D6
8
read-write
n
0x0
0x0
USB_RXCSRL13_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL13_DATAERR
Data Error
3
4
USB_RXCSRL13_ERROR
Error
2
3
USB_RXCSRL13_FLUSH
Flush FIFO
4
5
USB_RXCSRL13_FULL
FIFO Full
1
2
USB_RXCSRL13_NAKTO
NAK Timeout
3
4
USB_RXCSRL13_OVER
Overrun
2
3
USB_RXCSRL13_REQPKT
Request Packet
5
6
USB_RXCSRL13_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL13_STALL
Send STALL
5
6
USB_RXCSRL13_STALLED
Endpoint Stalled
6
7
RXCSRL14
USB Receive Control and Status Endpoint 14 Low
0x1E6
8
read-write
n
0x0
0x0
USB_RXCSRL14_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL14_DATAERR
Data Error
3
4
USB_RXCSRL14_ERROR
Error
2
3
USB_RXCSRL14_FLUSH
Flush FIFO
4
5
USB_RXCSRL14_FULL
FIFO Full
1
2
USB_RXCSRL14_NAKTO
NAK Timeout
3
4
USB_RXCSRL14_OVER
Overrun
2
3
USB_RXCSRL14_REQPKT
Request Packet
5
6
USB_RXCSRL14_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL14_STALL
Send STALL
5
6
USB_RXCSRL14_STALLED
Endpoint Stalled
6
7
RXCSRL15
USB Receive Control and Status Endpoint 15 Low
0x1F6
8
read-write
n
0x0
0x0
USB_RXCSRL15_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL15_DATAERR
Data Error
3
4
USB_RXCSRL15_ERROR
Error
2
3
USB_RXCSRL15_FLUSH
Flush FIFO
4
5
USB_RXCSRL15_FULL
FIFO Full
1
2
USB_RXCSRL15_NAKTO
NAK Timeout
3
4
USB_RXCSRL15_OVER
Overrun
2
3
USB_RXCSRL15_REQPKT
Request Packet
5
6
USB_RXCSRL15_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL15_STALL
Send STALL
5
6
USB_RXCSRL15_STALLED
Endpoint Stalled
6
7
RXCSRL2
USB Receive Control and Status Endpoint 2 Low
0x126
8
read-write
n
0x0
0x0
USB_RXCSRL2_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL2_DATAERR
Data Error
3
4
USB_RXCSRL2_ERROR
Error
2
3
USB_RXCSRL2_FLUSH
Flush FIFO
4
5
USB_RXCSRL2_FULL
FIFO Full
1
2
USB_RXCSRL2_NAKTO
NAK Timeout
3
4
USB_RXCSRL2_OVER
Overrun
2
3
USB_RXCSRL2_REQPKT
Request Packet
5
6
USB_RXCSRL2_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL2_STALL
Send STALL
5
6
USB_RXCSRL2_STALLED
Endpoint Stalled
6
7
RXCSRL3
USB Receive Control and Status Endpoint 3 Low
0x136
8
read-write
n
0x0
0x0
USB_RXCSRL3_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL3_DATAERR
Data Error
3
4
USB_RXCSRL3_ERROR
Error
2
3
USB_RXCSRL3_FLUSH
Flush FIFO
4
5
USB_RXCSRL3_FULL
FIFO Full
1
2
USB_RXCSRL3_NAKTO
NAK Timeout
3
4
USB_RXCSRL3_OVER
Overrun
2
3
USB_RXCSRL3_REQPKT
Request Packet
5
6
USB_RXCSRL3_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL3_STALL
Send STALL
5
6
USB_RXCSRL3_STALLED
Endpoint Stalled
6
7
RXCSRL4
USB Receive Control and Status Endpoint 4 Low
0x146
8
read-write
n
0x0
0x0
USB_RXCSRL4_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL4_DATAERR
Data Error
3
4
USB_RXCSRL4_ERROR
Error
2
3
USB_RXCSRL4_FLUSH
Flush FIFO
4
5
USB_RXCSRL4_FULL
FIFO Full
1
2
USB_RXCSRL4_NAKTO
NAK Timeout
3
4
USB_RXCSRL4_OVER
Overrun
2
3
USB_RXCSRL4_REQPKT
Request Packet
5
6
USB_RXCSRL4_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL4_STALL
Send STALL
5
6
USB_RXCSRL4_STALLED
Endpoint Stalled
6
7
RXCSRL5
USB Receive Control and Status Endpoint 5 Low
0x156
8
read-write
n
0x0
0x0
USB_RXCSRL5_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL5_DATAERR
Data Error
3
4
USB_RXCSRL5_ERROR
Error
2
3
USB_RXCSRL5_FLUSH
Flush FIFO
4
5
USB_RXCSRL5_FULL
FIFO Full
1
2
USB_RXCSRL5_NAKTO
NAK Timeout
3
4
USB_RXCSRL5_OVER
Overrun
2
3
USB_RXCSRL5_REQPKT
Request Packet
5
6
USB_RXCSRL5_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL5_STALL
Send STALL
5
6
USB_RXCSRL5_STALLED
Endpoint Stalled
6
7
RXCSRL6
USB Receive Control and Status Endpoint 6 Low
0x166
8
read-write
n
0x0
0x0
USB_RXCSRL6_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL6_DATAERR
Data Error
3
4
USB_RXCSRL6_ERROR
Error
2
3
USB_RXCSRL6_FLUSH
Flush FIFO
4
5
USB_RXCSRL6_FULL
FIFO Full
1
2
USB_RXCSRL6_NAKTO
NAK Timeout
3
4
USB_RXCSRL6_OVER
Overrun
2
3
USB_RXCSRL6_REQPKT
Request Packet
5
6
USB_RXCSRL6_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL6_STALL
Send STALL
5
6
USB_RXCSRL6_STALLED
Endpoint Stalled
6
7
RXCSRL7
USB Receive Control and Status Endpoint 7 Low
0x176
8
read-write
n
0x0
0x0
USB_RXCSRL7_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL7_DATAERR
Data Error
3
4
USB_RXCSRL7_ERROR
Error
2
3
USB_RXCSRL7_FLUSH
Flush FIFO
4
5
USB_RXCSRL7_FULL
FIFO Full
1
2
USB_RXCSRL7_NAKTO
NAK Timeout
3
4
USB_RXCSRL7_OVER
Overrun
2
3
USB_RXCSRL7_REQPKT
Request Packet
5
6
USB_RXCSRL7_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL7_STALL
Send STALL
5
6
USB_RXCSRL7_STALLED
Endpoint Stalled
6
7
RXCSRL8
USB Receive Control and Status Endpoint 8 Low
0x186
8
read-write
n
0x0
0x0
USB_RXCSRL8_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL8_DATAERR
Data Error
3
4
USB_RXCSRL8_ERROR
Error
2
3
USB_RXCSRL8_FLUSH
Flush FIFO
4
5
USB_RXCSRL8_FULL
FIFO Full
1
2
USB_RXCSRL8_NAKTO
NAK Timeout
3
4
USB_RXCSRL8_OVER
Overrun
2
3
USB_RXCSRL8_REQPKT
Request Packet
5
6
USB_RXCSRL8_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL8_STALL
Send STALL
5
6
USB_RXCSRL8_STALLED
Endpoint Stalled
6
7
RXCSRL9
USB Receive Control and Status Endpoint 9 Low
0x196
8
read-write
n
0x0
0x0
USB_RXCSRL9_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL9_DATAERR
Data Error
3
4
USB_RXCSRL9_ERROR
Error
2
3
USB_RXCSRL9_FLUSH
Flush FIFO
4
5
USB_RXCSRL9_FULL
FIFO Full
1
2
USB_RXCSRL9_NAKTO
NAK Timeout
3
4
USB_RXCSRL9_OVER
Overrun
2
3
USB_RXCSRL9_REQPKT
Request Packet
5
6
USB_RXCSRL9_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL9_STALL
Send STALL
5
6
USB_RXCSRL9_STALLED
Endpoint Stalled
6
7
RXDPKTBUFDIS
USB Receive Double Packet Buffer Disable
0x340
16
read-write
n
0x0
0x0
USB_RXDPKTBUFDIS_EP1
EP1 RX Double-Packet Buffer Disable
1
2
USB_RXDPKTBUFDIS_EP10
EP10 RX Double-Packet Buffer Disable
10
11
USB_RXDPKTBUFDIS_EP11
EP11 RX Double-Packet Buffer Disable
11
12
USB_RXDPKTBUFDIS_EP12
EP12 RX Double-Packet Buffer Disable
12
13
USB_RXDPKTBUFDIS_EP13
EP13 RX Double-Packet Buffer Disable
13
14
USB_RXDPKTBUFDIS_EP14
EP14 RX Double-Packet Buffer Disable
14
15
USB_RXDPKTBUFDIS_EP15
EP15 RX Double-Packet Buffer Disable
15
16
USB_RXDPKTBUFDIS_EP2
EP2 RX Double-Packet Buffer Disable
2
3
USB_RXDPKTBUFDIS_EP3
EP3 RX Double-Packet Buffer Disable
3
4
USB_RXDPKTBUFDIS_EP4
EP4 RX Double-Packet Buffer Disable
4
5
USB_RXDPKTBUFDIS_EP5
EP5 RX Double-Packet Buffer Disable
5
6
USB_RXDPKTBUFDIS_EP6
EP6 RX Double-Packet Buffer Disable
6
7
USB_RXDPKTBUFDIS_EP7
EP7 RX Double-Packet Buffer Disable
7
8
USB_RXDPKTBUFDIS_EP8
EP8 RX Double-Packet Buffer Disable
8
9
USB_RXDPKTBUFDIS_EP9
EP9 RX Double-Packet Buffer Disable
9
10
RXFIFOADD
USB Receive FIFO Start Address
0x66
16
read-write
n
0x0
0x0
USB_RXFIFOADD_ADDR
Transmit/Receive Start Address
0
9
RXFIFOSZ
USB Receive Dynamic FIFO Sizing
0x63
8
read-write
n
0x0
0x0
USB_RXFIFOSZ_DPB
Double Packet Buffer Support
4
5
USB_RXFIFOSZ_SIZE
Max Packet Size
0
4
USB_RXFIFOSZ_SIZE_8
8
0x0
USB_RXFIFOSZ_SIZE_16
16
0x1
USB_RXFIFOSZ_SIZE_32
32
0x2
USB_RXFIFOSZ_SIZE_64
64
0x3
USB_RXFIFOSZ_SIZE_128
128
0x4
USB_RXFIFOSZ_SIZE_256
256
0x5
USB_RXFIFOSZ_SIZE_512
512
0x6
USB_RXFIFOSZ_SIZE_1024
1024
0x7
USB_RXFIFOSZ_SIZE_2048
2048
0x8
RXFUNCADDR1
USB Receive Functional Address Endpoint 1
0x8C
8
read-write
n
0x0
0x0
USB_RXFUNCADDR1_ADDR
Device Address
0
7
RXFUNCADDR10
USB Receive Functional Address Endpoint 10
0xD4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR10_ADDR
Device Address
0
7
RXFUNCADDR11
USB Receive Functional Address Endpoint 11
0xDC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR11_ADDR
Device Address
0
7
RXFUNCADDR12
USB Receive Functional Address Endpoint 12
0xE4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR12_ADDR
Device Address
0
7
RXFUNCADDR13
USB Receive Functional Address Endpoint 13
0xEC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR13_ADDR
Device Address
0
7
RXFUNCADDR14
USB Receive Functional Address Endpoint 14
0xF4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR14_ADDR
Device Address
0
7
RXFUNCADDR15
USB Receive Functional Address Endpoint 15
0xFC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR15_ADDR
Device Address
0
7
RXFUNCADDR2
USB Receive Functional Address Endpoint 2
0x94
8
read-write
n
0x0
0x0
USB_RXFUNCADDR2_ADDR
Device Address
0
7
RXFUNCADDR3
USB Receive Functional Address Endpoint 3
0x9C
8
read-write
n
0x0
0x0
USB_RXFUNCADDR3_ADDR
Device Address
0
7
RXFUNCADDR4
USB Receive Functional Address Endpoint 4
0xA4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR4_ADDR
Device Address
0
7
RXFUNCADDR5
USB Receive Functional Address Endpoint 5
0xAC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR5_ADDR
Device Address
0
7
RXFUNCADDR6
USB Receive Functional Address Endpoint 6
0xB4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR6_ADDR
Device Address
0
7
RXFUNCADDR7
USB Receive Functional Address Endpoint 7
0xBC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR7_ADDR
Device Address
0
7
RXFUNCADDR8
USB Receive Functional Address Endpoint 8
0xC4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR8_ADDR
Device Address
0
7
RXFUNCADDR9
USB Receive Functional Address Endpoint 9
0xCC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR9_ADDR
Device Address
0
7
RXHUBADDR1
USB Receive Hub Address Endpoint 1
0x8E
8
read-write
n
0x0
0x0
USB_RXHUBADDR1_ADDR
Hub Address
0
7
USB_RXHUBADDR1_MULTTRAN
Multiple Translators
7
8
RXHUBADDR10
USB Receive Hub Address Endpoint 10
0xD6
8
read-write
n
0x0
0x0
USB_RXHUBADDR10_ADDR
Hub Address
0
7
USB_RXHUBADDR10_MULTTRAN
Multiple Translators
7
8
RXHUBADDR11
USB Receive Hub Address Endpoint 11
0xDE
8
read-write
n
0x0
0x0
USB_RXHUBADDR11_ADDR
Hub Address
0
7
USB_RXHUBADDR11_MULTTRAN
Multiple Translators
7
8
RXHUBADDR12
USB Receive Hub Address Endpoint 12
0xE6
8
read-write
n
0x0
0x0
USB_RXHUBADDR12_ADDR
Hub Address
0
7
USB_RXHUBADDR12_MULTTRAN
Multiple Translators
7
8
RXHUBADDR13
USB Receive Hub Address Endpoint 13
0xEE
8
read-write
n
0x0
0x0
USB_RXHUBADDR13_ADDR
Hub Address
0
7
USB_RXHUBADDR13_MULTTRAN
Multiple Translators
7
8
RXHUBADDR14
USB Receive Hub Address Endpoint 14
0xF6
8
read-write
n
0x0
0x0
USB_RXHUBADDR14_ADDR
Hub Address
0
7
USB_RXHUBADDR14_MULTTRAN
Multiple Translators
7
8
RXHUBADDR15
USB Receive Hub Address Endpoint 15
0xFE
8
read-write
n
0x0
0x0
USB_RXHUBADDR15_ADDR
Hub Address
0
7
USB_RXHUBADDR15_MULTTRAN
Multiple Translators
7
8
RXHUBADDR2
USB Receive Hub Address Endpoint 2
0x96
8
read-write
n
0x0
0x0
USB_RXHUBADDR2_ADDR
Hub Address
0
7
USB_RXHUBADDR2_MULTTRAN
Multiple Translators
7
8
RXHUBADDR3
USB Receive Hub Address Endpoint 3
0x9E
8
read-write
n
0x0
0x0
USB_RXHUBADDR3_ADDR
Hub Address
0
7
USB_RXHUBADDR3_MULTTRAN
Multiple Translators
7
8
RXHUBADDR4
USB Receive Hub Address Endpoint 4
0xA6
8
read-write
n
0x0
0x0
USB_RXHUBADDR4_ADDR
Hub Address
0
7
USB_RXHUBADDR4_MULTTRAN
Multiple Translators
7
8
RXHUBADDR5
USB Receive Hub Address Endpoint 5
0xAE
8
read-write
n
0x0
0x0
USB_RXHUBADDR5_ADDR
Hub Address
0
7
USB_RXHUBADDR5_MULTTRAN
Multiple Translators
7
8
RXHUBADDR6
USB Receive Hub Address Endpoint 6
0xB6
8
read-write
n
0x0
0x0
USB_RXHUBADDR6_ADDR
Hub Address
0
7
USB_RXHUBADDR6_MULTTRAN
Multiple Translators
7
8
RXHUBADDR7
USB Receive Hub Address Endpoint 7
0xBE
8
read-write
n
0x0
0x0
USB_RXHUBADDR7_ADDR
Hub Address
0
7
USB_RXHUBADDR7_MULTTRAN
Multiple Translators
7
8
RXHUBADDR8
USB Receive Hub Address Endpoint 8
0xC6
8
read-write
n
0x0
0x0
USB_RXHUBADDR8_ADDR
Hub Address
0
7
USB_RXHUBADDR8_MULTTRAN
Multiple Translators
7
8
RXHUBADDR9
USB Receive Hub Address Endpoint 9
0xCE
8
read-write
n
0x0
0x0
USB_RXHUBADDR9_ADDR
Hub Address
0
7
USB_RXHUBADDR9_MULTTRAN
Multiple Translators
7
8
RXHUBPORT1
USB Receive Hub Port Endpoint 1
0x8F
8
read-write
n
0x0
0x0
USB_RXHUBPORT1_PORT
Hub Port
0
7
RXHUBPORT10
USB Receive Hub Port Endpoint 10
0xD7
8
read-write
n
0x0
0x0
USB_RXHUBPORT10_PORT
Hub Port
0
7
RXHUBPORT11
USB Receive Hub Port Endpoint 11
0xDF
8
read-write
n
0x0
0x0
USB_RXHUBPORT11_PORT
Hub Port
0
7
RXHUBPORT12
USB Receive Hub Port Endpoint 12
0xE7
8
read-write
n
0x0
0x0
USB_RXHUBPORT12_PORT
Hub Port
0
7
RXHUBPORT13
USB Receive Hub Port Endpoint 13
0xEF
8
read-write
n
0x0
0x0
USB_RXHUBPORT13_PORT
Hub Port
0
7
RXHUBPORT14
USB Receive Hub Port Endpoint 14
0xF7
8
read-write
n
0x0
0x0
USB_RXHUBPORT14_PORT
Hub Port
0
7
RXHUBPORT15
USB Receive Hub Port Endpoint 15
0xFF
8
read-write
n
0x0
0x0
USB_RXHUBPORT15_PORT
Hub Port
0
7
RXHUBPORT2
USB Receive Hub Port Endpoint 2
0x97
8
read-write
n
0x0
0x0
USB_RXHUBPORT2_PORT
Hub Port
0
7
RXHUBPORT3
USB Receive Hub Port Endpoint 3
0x9F
8
read-write
n
0x0
0x0
USB_RXHUBPORT3_PORT
Hub Port
0
7
RXHUBPORT4
USB Receive Hub Port Endpoint 4
0xA7
8
read-write
n
0x0
0x0
USB_RXHUBPORT4_PORT
Hub Port
0
7
RXHUBPORT5
USB Receive Hub Port Endpoint 5
0xAF
8
read-write
n
0x0
0x0
USB_RXHUBPORT5_PORT
Hub Port
0
7
RXHUBPORT6
USB Receive Hub Port Endpoint 6
0xB7
8
read-write
n
0x0
0x0
USB_RXHUBPORT6_PORT
Hub Port
0
7
RXHUBPORT7
USB Receive Hub Port Endpoint 7
0xBF
8
read-write
n
0x0
0x0
USB_RXHUBPORT7_PORT
Hub Port
0
7
RXHUBPORT8
USB Receive Hub Port Endpoint 8
0xC7
8
read-write
n
0x0
0x0
USB_RXHUBPORT8_PORT
Hub Port
0
7
RXHUBPORT9
USB Receive Hub Port Endpoint 9
0xCF
8
read-write
n
0x0
0x0
USB_RXHUBPORT9_PORT
Hub Port
0
7
RXIE
USB Receive Interrupt Enable
0x8
16
read-write
n
0x0
0x0
USB_RXIE_EP1
RX Endpoint 1 Interrupt Enable
1
2
USB_RXIE_EP10
RX Endpoint 10 Interrupt Enable
10
11
USB_RXIE_EP11
RX Endpoint 11 Interrupt Enable
11
12
USB_RXIE_EP12
RX Endpoint 12 Interrupt Enable
12
13
USB_RXIE_EP13
RX Endpoint 13 Interrupt Enable
13
14
USB_RXIE_EP14
RX Endpoint 14 Interrupt Enable
14
15
USB_RXIE_EP15
RX Endpoint 15 Interrupt Enable
15
16
USB_RXIE_EP2
RX Endpoint 2 Interrupt Enable
2
3
USB_RXIE_EP3
RX Endpoint 3 Interrupt Enable
3
4
USB_RXIE_EP4
RX Endpoint 4 Interrupt Enable
4
5
USB_RXIE_EP5
RX Endpoint 5 Interrupt Enable
5
6
USB_RXIE_EP6
RX Endpoint 6 Interrupt Enable
6
7
USB_RXIE_EP7
RX Endpoint 7 Interrupt Enable
7
8
USB_RXIE_EP8
RX Endpoint 8 Interrupt Enable
8
9
USB_RXIE_EP9
RX Endpoint 9 Interrupt Enable
9
10
RXINTERVAL1
USB Host Receive Polling Interval Endpoint 1
0x11D
8
read-write
n
0x0
0x0
USB_RXINTERVAL1_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL1_TXPOLL
RX Polling
0
8
RXINTERVAL10
USB Host Receive Polling Interval Endpoint 10
0x1AD
8
read-write
n
0x0
0x0
USB_RXINTERVAL10_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL10_TXPOLL
RX Polling
0
8
RXINTERVAL11
USB Host Receive Polling Interval Endpoint 11
0x1BD
8
read-write
n
0x0
0x0
USB_RXINTERVAL11_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL11_TXPOLL
RX Polling
0
8
RXINTERVAL12
USB Host Receive Polling Interval Endpoint 12
0x1CD
8
read-write
n
0x0
0x0
USB_RXINTERVAL12_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL12_TXPOLL
RX Polling
0
8
RXINTERVAL13
USB Host Receive Polling Interval Endpoint 13
0x1DD
8
read-write
n
0x0
0x0
USB_RXINTERVAL13_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL13_TXPOLL
RX Polling
0
8
RXINTERVAL14
USB Host Receive Polling Interval Endpoint 14
0x1ED
8
read-write
n
0x0
0x0
USB_RXINTERVAL14_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL14_TXPOLL
RX Polling
0
8
RXINTERVAL15
USB Host Receive Polling Interval Endpoint 15
0x1FD
8
read-write
n
0x0
0x0
USB_RXINTERVAL15_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL15_TXPOLL
RX Polling
0
8
RXINTERVAL2
USB Host Receive Polling Interval Endpoint 2
0x12D
8
read-write
n
0x0
0x0
USB_RXINTERVAL2_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL2_TXPOLL
RX Polling
0
8
RXINTERVAL3
USB Host Receive Polling Interval Endpoint 3
0x13D
8
read-write
n
0x0
0x0
USB_RXINTERVAL3_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL3_TXPOLL
RX Polling
0
8
RXINTERVAL4
USB Host Receive Polling Interval Endpoint 4
0x14D
8
read-write
n
0x0
0x0
USB_RXINTERVAL4_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL4_TXPOLL
RX Polling
0
8
RXINTERVAL5
USB Host Receive Polling Interval Endpoint 5
0x15D
8
read-write
n
0x0
0x0
USB_RXINTERVAL5_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL5_TXPOLL
RX Polling
0
8
RXINTERVAL6
USB Host Receive Polling Interval Endpoint 6
0x16D
8
read-write
n
0x0
0x0
USB_RXINTERVAL6_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL6_TXPOLL
RX Polling
0
8
RXINTERVAL7
USB Host Receive Polling Interval Endpoint 7
0x17D
8
read-write
n
0x0
0x0
USB_RXINTERVAL7_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL7_TXPOLL
RX Polling
0
8
RXINTERVAL8
USB Host Receive Polling Interval Endpoint 8
0x18D
8
read-write
n
0x0
0x0
USB_RXINTERVAL8_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL8_TXPOLL
RX Polling
0
8
RXINTERVAL9
USB Host Receive Polling Interval Endpoint 9
0x19D
8
read-write
n
0x0
0x0
USB_RXINTERVAL9_NAKLMT
NAK Limit
0
8
USB_RXINTERVAL9_TXPOLL
RX Polling
0
8
RXIS
USB Receive Interrupt Status
0x4
16
read-write
n
0x0
0x0
USB_RXIS_EP1
RX Endpoint 1 Interrupt
1
2
USB_RXIS_EP10
RX Endpoint 10 Interrupt
10
11
USB_RXIS_EP11
RX Endpoint 11 Interrupt
11
12
USB_RXIS_EP12
RX Endpoint 12 Interrupt
12
13
USB_RXIS_EP13
RX Endpoint 13 Interrupt
13
14
USB_RXIS_EP14
RX Endpoint 14 Interrupt
14
15
USB_RXIS_EP15
RX Endpoint 15 Interrupt
15
16
USB_RXIS_EP2
RX Endpoint 2 Interrupt
2
3
USB_RXIS_EP3
RX Endpoint 3 Interrupt
3
4
USB_RXIS_EP4
RX Endpoint 4 Interrupt
4
5
USB_RXIS_EP5
RX Endpoint 5 Interrupt
5
6
USB_RXIS_EP6
RX Endpoint 6 Interrupt
6
7
USB_RXIS_EP7
RX Endpoint 7 Interrupt
7
8
USB_RXIS_EP8
RX Endpoint 8 Interrupt
8
9
USB_RXIS_EP9
RX Endpoint 9 Interrupt
9
10
RXMAXP1
USB Maximum Receive Data Endpoint 1
0x114
16
read-write
n
0x0
0x0
USB_RXMAXP1_MAXLOAD
Maximum Payload
0
11
RXMAXP10
USB Maximum Receive Data Endpoint 10
0x1A4
16
read-write
n
0x0
0x0
USB_RXMAXP10_MAXLOAD
Maximum Payload
0
11
RXMAXP11
USB Maximum Receive Data Endpoint 11
0x1B4
16
read-write
n
0x0
0x0
USB_RXMAXP11_MAXLOAD
Maximum Payload
0
11
RXMAXP12
USB Maximum Receive Data Endpoint 12
0x1C4
16
read-write
n
0x0
0x0
USB_RXMAXP12_MAXLOAD
Maximum Payload
0
11
RXMAXP13
USB Maximum Receive Data Endpoint 13
0x1D4
16
read-write
n
0x0
0x0
USB_RXMAXP13_MAXLOAD
Maximum Payload
0
11
RXMAXP14
USB Maximum Receive Data Endpoint 14
0x1E4
16
read-write
n
0x0
0x0
USB_RXMAXP14_MAXLOAD
Maximum Payload
0
11
RXMAXP15
USB Maximum Receive Data Endpoint 15
0x1F4
16
read-write
n
0x0
0x0
USB_RXMAXP15_MAXLOAD
Maximum Payload
0
11
RXMAXP2
USB Maximum Receive Data Endpoint 2
0x124
16
read-write
n
0x0
0x0
USB_RXMAXP2_MAXLOAD
Maximum Payload
0
11
RXMAXP3
USB Maximum Receive Data Endpoint 3
0x134
16
read-write
n
0x0
0x0
USB_RXMAXP3_MAXLOAD
Maximum Payload
0
11
RXMAXP4
USB Maximum Receive Data Endpoint 4
0x144
16
read-write
n
0x0
0x0
USB_RXMAXP4_MAXLOAD
Maximum Payload
0
11
RXMAXP5
USB Maximum Receive Data Endpoint 5
0x154
16
read-write
n
0x0
0x0
USB_RXMAXP5_MAXLOAD
Maximum Payload
0
11
RXMAXP6
USB Maximum Receive Data Endpoint 6
0x164
16
read-write
n
0x0
0x0
USB_RXMAXP6_MAXLOAD
Maximum Payload
0
11
RXMAXP7
USB Maximum Receive Data Endpoint 7
0x174
16
read-write
n
0x0
0x0
USB_RXMAXP7_MAXLOAD
Maximum Payload
0
11
RXMAXP8
USB Maximum Receive Data Endpoint 8
0x184
16
read-write
n
0x0
0x0
USB_RXMAXP8_MAXLOAD
Maximum Payload
0
11
RXMAXP9
USB Maximum Receive Data Endpoint 9
0x194
16
read-write
n
0x0
0x0
USB_RXMAXP9_MAXLOAD
Maximum Payload
0
11
RXTYPE1
USB Host Configure Receive Type Endpoint 1
0x11C
8
read-write
n
0x0
0x0
USB_RXTYPE1_PROTO
Protocol
4
6
USB_RXTYPE1_PROTO_CTRL
Control
0x0
USB_RXTYPE1_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE1_PROTO_BULK
Bulk
0x2
USB_RXTYPE1_PROTO_INT
Interrupt
0x3
USB_RXTYPE1_SPEED
Operating Speed
6
8
USB_RXTYPE1_SPEED_DFLT
Default
0x0
USB_RXTYPE1_SPEED_FULL
Full
0x2
USB_RXTYPE1_SPEED_LOW
Low
0x3
USB_RXTYPE1_TEP
Target Endpoint Number
0
4
RXTYPE10
USB Host Configure Receive Type Endpoint 10
0x1AC
8
read-write
n
0x0
0x0
USB_RXTYPE10_PROTO
Protocol
4
6
USB_RXTYPE10_PROTO_CTRL
Control
0x0
USB_RXTYPE10_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE10_PROTO_BULK
Bulk
0x2
USB_RXTYPE10_PROTO_INT
Interrupt
0x3
USB_RXTYPE10_SPEED
Operating Speed
6
8
USB_RXTYPE10_SPEED_DFLT
Default
0x0
USB_RXTYPE10_SPEED_FULL
Full
0x2
USB_RXTYPE10_SPEED_LOW
Low
0x3
USB_RXTYPE10_TEP
Target Endpoint Number
0
4
RXTYPE11
USB Host Configure Receive Type Endpoint 11
0x1BC
8
read-write
n
0x0
0x0
USB_RXTYPE11_PROTO
Protocol
4
6
USB_RXTYPE11_PROTO_CTRL
Control
0x0
USB_RXTYPE11_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE11_PROTO_BULK
Bulk
0x2
USB_RXTYPE11_PROTO_INT
Interrupt
0x3
USB_RXTYPE11_SPEED
Operating Speed
6
8
USB_RXTYPE11_SPEED_DFLT
Default
0x0
USB_RXTYPE11_SPEED_FULL
Full
0x2
USB_RXTYPE11_SPEED_LOW
Low
0x3
USB_RXTYPE11_TEP
Target Endpoint Number
0
4
RXTYPE12
USB Host Configure Receive Type Endpoint 12
0x1CC
8
read-write
n
0x0
0x0
USB_RXTYPE12_PROTO
Protocol
4
6
USB_RXTYPE12_PROTO_CTRL
Control
0x0
USB_RXTYPE12_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE12_PROTO_BULK
Bulk
0x2
USB_RXTYPE12_PROTO_INT
Interrupt
0x3
USB_RXTYPE12_SPEED
Operating Speed
6
8
USB_RXTYPE12_SPEED_DFLT
Default
0x0
USB_RXTYPE12_SPEED_FULL
Full
0x2
USB_RXTYPE12_SPEED_LOW
Low
0x3
USB_RXTYPE12_TEP
Target Endpoint Number
0
4
RXTYPE13
USB Host Configure Receive Type Endpoint 13
0x1DC
8
read-write
n
0x0
0x0
USB_RXTYPE13_PROTO
Protocol
4
6
USB_RXTYPE13_PROTO_CTRL
Control
0x0
USB_RXTYPE13_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE13_PROTO_BULK
Bulk
0x2
USB_RXTYPE13_PROTO_INT
Interrupt
0x3
USB_RXTYPE13_SPEED
Operating Speed
6
8
USB_RXTYPE13_SPEED_DFLT
Default
0x0
USB_RXTYPE13_SPEED_FULL
Full
0x2
USB_RXTYPE13_SPEED_LOW
Low
0x3
USB_RXTYPE13_TEP
Target Endpoint Number
0
4
RXTYPE14
USB Host Configure Receive Type Endpoint 14
0x1EC
8
read-write
n
0x0
0x0
USB_RXTYPE14_PROTO
Protocol
4
6
USB_RXTYPE14_PROTO_CTRL
Control
0x0
USB_RXTYPE14_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE14_PROTO_BULK
Bulk
0x2
USB_RXTYPE14_PROTO_INT
Interrupt
0x3
USB_RXTYPE14_SPEED
Operating Speed
6
8
USB_RXTYPE14_SPEED_DFLT
Default
0x0
USB_RXTYPE14_SPEED_FULL
Full
0x2
USB_RXTYPE14_SPEED_LOW
Low
0x3
USB_RXTYPE14_TEP
Target Endpoint Number
0
4
RXTYPE15
USB Host Configure Receive Type Endpoint 15
0x1FC
8
read-write
n
0x0
0x0
USB_RXTYPE15_PROTO
Protocol
4
6
USB_RXTYPE15_PROTO_CTRL
Control
0x0
USB_RXTYPE15_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE15_PROTO_BULK
Bulk
0x2
USB_RXTYPE15_PROTO_INT
Interrupt
0x3
USB_RXTYPE15_SPEED
Operating Speed
6
8
USB_RXTYPE15_SPEED_DFLT
Default
0x0
USB_RXTYPE15_SPEED_FULL
Full
0x2
USB_RXTYPE15_SPEED_LOW
Low
0x3
USB_RXTYPE15_TEP
Target Endpoint Number
0
4
RXTYPE2
USB Host Configure Receive Type Endpoint 2
0x12C
8
read-write
n
0x0
0x0
USB_RXTYPE2_PROTO
Protocol
4
6
USB_RXTYPE2_PROTO_CTRL
Control
0x0
USB_RXTYPE2_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE2_PROTO_BULK
Bulk
0x2
USB_RXTYPE2_PROTO_INT
Interrupt
0x3
USB_RXTYPE2_SPEED
Operating Speed
6
8
USB_RXTYPE2_SPEED_DFLT
Default
0x0
USB_RXTYPE2_SPEED_FULL
Full
0x2
USB_RXTYPE2_SPEED_LOW
Low
0x3
USB_RXTYPE2_TEP
Target Endpoint Number
0
4
RXTYPE3
USB Host Configure Receive Type Endpoint 3
0x13C
8
read-write
n
0x0
0x0
USB_RXTYPE3_PROTO
Protocol
4
6
USB_RXTYPE3_PROTO_CTRL
Control
0x0
USB_RXTYPE3_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE3_PROTO_BULK
Bulk
0x2
USB_RXTYPE3_PROTO_INT
Interrupt
0x3
USB_RXTYPE3_SPEED
Operating Speed
6
8
USB_RXTYPE3_SPEED_DFLT
Default
0x0
USB_RXTYPE3_SPEED_FULL
Full
0x2
USB_RXTYPE3_SPEED_LOW
Low
0x3
USB_RXTYPE3_TEP
Target Endpoint Number
0
4
RXTYPE4
USB Host Configure Receive Type Endpoint 4
0x14C
8
read-write
n
0x0
0x0
USB_RXTYPE4_PROTO
Protocol
4
6
USB_RXTYPE4_PROTO_CTRL
Control
0x0
USB_RXTYPE4_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE4_PROTO_BULK
Bulk
0x2
USB_RXTYPE4_PROTO_INT
Interrupt
0x3
USB_RXTYPE4_SPEED
Operating Speed
6
8
USB_RXTYPE4_SPEED_DFLT
Default
0x0
USB_RXTYPE4_SPEED_FULL
Full
0x2
USB_RXTYPE4_SPEED_LOW
Low
0x3
USB_RXTYPE4_TEP
Target Endpoint Number
0
4
RXTYPE5
USB Host Configure Receive Type Endpoint 5
0x15C
8
read-write
n
0x0
0x0
USB_RXTYPE5_PROTO
Protocol
4
6
USB_RXTYPE5_PROTO_CTRL
Control
0x0
USB_RXTYPE5_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE5_PROTO_BULK
Bulk
0x2
USB_RXTYPE5_PROTO_INT
Interrupt
0x3
USB_RXTYPE5_SPEED
Operating Speed
6
8
USB_RXTYPE5_SPEED_DFLT
Default
0x0
USB_RXTYPE5_SPEED_FULL
Full
0x2
USB_RXTYPE5_SPEED_LOW
Low
0x3
USB_RXTYPE5_TEP
Target Endpoint Number
0
4
RXTYPE6
USB Host Configure Receive Type Endpoint 6
0x16C
8
read-write
n
0x0
0x0
USB_RXTYPE6_PROTO
Protocol
4
6
USB_RXTYPE6_PROTO_CTRL
Control
0x0
USB_RXTYPE6_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE6_PROTO_BULK
Bulk
0x2
USB_RXTYPE6_PROTO_INT
Interrupt
0x3
USB_RXTYPE6_SPEED
Operating Speed
6
8
USB_RXTYPE6_SPEED_DFLT
Default
0x0
USB_RXTYPE6_SPEED_FULL
Full
0x2
USB_RXTYPE6_SPEED_LOW
Low
0x3
USB_RXTYPE6_TEP
Target Endpoint Number
0
4
RXTYPE7
USB Host Configure Receive Type Endpoint 7
0x17C
8
read-write
n
0x0
0x0
USB_RXTYPE7_PROTO
Protocol
4
6
USB_RXTYPE7_PROTO_CTRL
Control
0x0
USB_RXTYPE7_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE7_PROTO_BULK
Bulk
0x2
USB_RXTYPE7_PROTO_INT
Interrupt
0x3
USB_RXTYPE7_SPEED
Operating Speed
6
8
USB_RXTYPE7_SPEED_DFLT
Default
0x0
USB_RXTYPE7_SPEED_FULL
Full
0x2
USB_RXTYPE7_SPEED_LOW
Low
0x3
USB_RXTYPE7_TEP
Target Endpoint Number
0
4
RXTYPE8
USB Host Configure Receive Type Endpoint 8
0x18C
8
read-write
n
0x0
0x0
USB_RXTYPE8_PROTO
Protocol
4
6
USB_RXTYPE8_PROTO_CTRL
Control
0x0
USB_RXTYPE8_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE8_PROTO_BULK
Bulk
0x2
USB_RXTYPE8_PROTO_INT
Interrupt
0x3
USB_RXTYPE8_SPEED
Operating Speed
6
8
USB_RXTYPE8_SPEED_DFLT
Default
0x0
USB_RXTYPE8_SPEED_FULL
Full
0x2
USB_RXTYPE8_SPEED_LOW
Low
0x3
USB_RXTYPE8_TEP
Target Endpoint Number
0
4
RXTYPE9
USB Host Configure Receive Type Endpoint 9
0x19C
8
read-write
n
0x0
0x0
USB_RXTYPE9_PROTO
Protocol
4
6
USB_RXTYPE9_PROTO_CTRL
Control
0x0
USB_RXTYPE9_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE9_PROTO_BULK
Bulk
0x2
USB_RXTYPE9_PROTO_INT
Interrupt
0x3
USB_RXTYPE9_SPEED
Operating Speed
6
8
USB_RXTYPE9_SPEED_DFLT
Default
0x0
USB_RXTYPE9_SPEED_FULL
Full
0x2
USB_RXTYPE9_SPEED_LOW
Low
0x3
USB_RXTYPE9_TEP
Target Endpoint Number
0
4
TEST
USB Test Mode
0xF
8
read-write
n
0x0
0x0
USB_TEST_FIFOACC
FIFO Access
6
7
USB_TEST_FORCEFS
Force Full-Speed Mode
5
6
USB_TEST_FORCEH
Force Host Mode
7
8
TXCSRH1
USB Transmit Control and Status Endpoint 1 High
0x113
8
read-write
n
0x0
0x0
USB_TXCSRH1_AUTOSET
Auto Set
7
8
USB_TXCSRH1_DMAEN
DMA Request Enable
4
5
USB_TXCSRH1_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH1_DT
Data Toggle
0
1
USB_TXCSRH1_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH1_FDT
Force Data Toggle
3
4
USB_TXCSRH1_ISO
Isochronous Transfers
6
7
USB_TXCSRH1_MODE
Mode
5
6
TXCSRH10
USB Transmit Control and Status Endpoint 10 High
0x1A3
8
read-write
n
0x0
0x0
USB_TXCSRH10_AUTOSET
Auto Set
7
8
USB_TXCSRH10_DMAEN
DMA Request Enable
4
5
USB_TXCSRH10_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH10_DT
Data Toggle
0
1
USB_TXCSRH10_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH10_FDT
Force Data Toggle
3
4
USB_TXCSRH10_ISO
Isochronous Transfers
6
7
USB_TXCSRH10_MODE
Mode
5
6
TXCSRH11
USB Transmit Control and Status Endpoint 11 High
0x1B3
8
read-write
n
0x0
0x0
USB_TXCSRH11_AUTOSET
Auto Set
7
8
USB_TXCSRH11_DMAEN
DMA Request Enable
4
5
USB_TXCSRH11_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH11_DT
Data Toggle
0
1
USB_TXCSRH11_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH11_FDT
Force Data Toggle
3
4
USB_TXCSRH11_ISO
Isochronous Transfers
6
7
USB_TXCSRH11_MODE
Mode
5
6
TXCSRH12
USB Transmit Control and Status Endpoint 12 High
0x1C3
8
read-write
n
0x0
0x0
USB_TXCSRH12_AUTOSET
Auto Set
7
8
USB_TXCSRH12_DMAEN
DMA Request Enable
4
5
USB_TXCSRH12_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH12_DT
Data Toggle
0
1
USB_TXCSRH12_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH12_FDT
Force Data Toggle
3
4
USB_TXCSRH12_ISO
Isochronous Transfers
6
7
USB_TXCSRH12_MODE
Mode
5
6
TXCSRH13
USB Transmit Control and Status Endpoint 13 High
0x1D3
8
read-write
n
0x0
0x0
USB_TXCSRH13_AUTOSET
Auto Set
7
8
USB_TXCSRH13_DMAEN
DMA Request Enable
4
5
USB_TXCSRH13_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH13_DT
Data Toggle
0
1
USB_TXCSRH13_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH13_FDT
Force Data Toggle
3
4
USB_TXCSRH13_ISO
Isochronous Transfers
6
7
USB_TXCSRH13_MODE
Mode
5
6
TXCSRH14
USB Transmit Control and Status Endpoint 14 High
0x1E3
8
read-write
n
0x0
0x0
USB_TXCSRH14_AUTOSET
Auto Set
7
8
USB_TXCSRH14_DMAEN
DMA Request Enable
4
5
USB_TXCSRH14_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH14_DT
Data Toggle
0
1
USB_TXCSRH14_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH14_FDT
Force Data Toggle
3
4
USB_TXCSRH14_ISO
Isochronous Transfers
6
7
USB_TXCSRH14_MODE
Mode
5
6
TXCSRH15
USB Transmit Control and Status Endpoint 15 High
0x1F3
8
read-write
n
0x0
0x0
USB_TXCSRH15_AUTOSET
Auto Set
7
8
USB_TXCSRH15_DMAEN
DMA Request Enable
4
5
USB_TXCSRH15_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH15_DT
Data Toggle
0
1
USB_TXCSRH15_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH15_FDT
Force Data Toggle
3
4
USB_TXCSRH15_ISO
Isochronous Transfers
6
7
USB_TXCSRH15_MODE
Mode
5
6
TXCSRH2
USB Transmit Control and Status Endpoint 2 High
0x123
8
read-write
n
0x0
0x0
USB_TXCSRH2_AUTOSET
Auto Set
7
8
USB_TXCSRH2_DMAEN
DMA Request Enable
4
5
USB_TXCSRH2_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH2_DT
Data Toggle
0
1
USB_TXCSRH2_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH2_FDT
Force Data Toggle
3
4
USB_TXCSRH2_ISO
Isochronous Transfers
6
7
USB_TXCSRH2_MODE
Mode
5
6
TXCSRH3
USB Transmit Control and Status Endpoint 3 High
0x133
8
read-write
n
0x0
0x0
USB_TXCSRH3_AUTOSET
Auto Set
7
8
USB_TXCSRH3_DMAEN
DMA Request Enable
4
5
USB_TXCSRH3_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH3_DT
Data Toggle
0
1
USB_TXCSRH3_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH3_FDT
Force Data Toggle
3
4
USB_TXCSRH3_ISO
Isochronous Transfers
6
7
USB_TXCSRH3_MODE
Mode
5
6
TXCSRH4
USB Transmit Control and Status Endpoint 4 High
0x143
8
read-write
n
0x0
0x0
USB_TXCSRH4_AUTOSET
Auto Set
7
8
USB_TXCSRH4_DMAEN
DMA Request Enable
4
5
USB_TXCSRH4_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH4_DT
Data Toggle
0
1
USB_TXCSRH4_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH4_FDT
Force Data Toggle
3
4
USB_TXCSRH4_ISO
Isochronous Transfers
6
7
USB_TXCSRH4_MODE
Mode
5
6
TXCSRH5
USB Transmit Control and Status Endpoint 5 High
0x153
8
read-write
n
0x0
0x0
USB_TXCSRH5_AUTOSET
Auto Set
7
8
USB_TXCSRH5_DMAEN
DMA Request Enable
4
5
USB_TXCSRH5_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH5_DT
Data Toggle
0
1
USB_TXCSRH5_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH5_FDT
Force Data Toggle
3
4
USB_TXCSRH5_ISO
Isochronous Transfers
6
7
USB_TXCSRH5_MODE
Mode
5
6
TXCSRH6
USB Transmit Control and Status Endpoint 6 High
0x163
8
read-write
n
0x0
0x0
USB_TXCSRH6_AUTOSET
Auto Set
7
8
USB_TXCSRH6_DMAEN
DMA Request Enable
4
5
USB_TXCSRH6_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH6_DT
Data Toggle
0
1
USB_TXCSRH6_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH6_FDT
Force Data Toggle
3
4
USB_TXCSRH6_ISO
Isochronous Transfers
6
7
USB_TXCSRH6_MODE
Mode
5
6
TXCSRH7
USB Transmit Control and Status Endpoint 7 High
0x173
8
read-write
n
0x0
0x0
USB_TXCSRH7_AUTOSET
Auto Set
7
8
USB_TXCSRH7_DMAEN
DMA Request Enable
4
5
USB_TXCSRH7_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH7_DT
Data Toggle
0
1
USB_TXCSRH7_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH7_FDT
Force Data Toggle
3
4
USB_TXCSRH7_ISO
Isochronous Transfers
6
7
USB_TXCSRH7_MODE
Mode
5
6
TXCSRH8
USB Transmit Control and Status Endpoint 8 High
0x183
8
read-write
n
0x0
0x0
USB_TXCSRH8_AUTOSET
Auto Set
7
8
USB_TXCSRH8_DMAEN
DMA Request Enable
4
5
USB_TXCSRH8_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH8_DT
Data Toggle
0
1
USB_TXCSRH8_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH8_FDT
Force Data Toggle
3
4
USB_TXCSRH8_ISO
Isochronous Transfers
6
7
USB_TXCSRH8_MODE
Mode
5
6
TXCSRH9
USB Transmit Control and Status Endpoint 9 High
0x193
8
read-write
n
0x0
0x0
USB_TXCSRH9_AUTOSET
Auto Set
7
8
USB_TXCSRH9_DMAEN
DMA Request Enable
4
5
USB_TXCSRH9_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH9_DT
Data Toggle
0
1
USB_TXCSRH9_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH9_FDT
Force Data Toggle
3
4
USB_TXCSRH9_ISO
Isochronous Transfers
6
7
USB_TXCSRH9_MODE
Mode
5
6
TXCSRL1
USB Transmit Control and Status Endpoint 1 Low
0x112
8
read-write
n
0x0
0x0
USB_TXCSRL1_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL1_ERROR
Error
2
3
USB_TXCSRL1_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL1_FLUSH
Flush FIFO
3
4
USB_TXCSRL1_NAKTO
NAK Timeout
7
8
USB_TXCSRL1_SETUP
Setup Packet
4
5
USB_TXCSRL1_STALL
Send STALL
4
5
USB_TXCSRL1_STALLED
Endpoint Stalled
5
6
USB_TXCSRL1_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL1_UNDRN
Underrun
2
3
TXCSRL10
USB Transmit Control and Status Endpoint 10 Low
0x1A2
8
read-write
n
0x0
0x0
USB_TXCSRL10_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL10_ERROR
Error
2
3
USB_TXCSRL10_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL10_FLUSH
Flush FIFO
3
4
USB_TXCSRL10_NAKTO
NAK Timeout
7
8
USB_TXCSRL10_SETUP
Setup Packet
4
5
USB_TXCSRL10_STALL
Send STALL
4
5
USB_TXCSRL10_STALLED
Endpoint Stalled
5
6
USB_TXCSRL10_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL10_UNDRN
Underrun
2
3
TXCSRL11
USB Transmit Control and Status Endpoint 11 Low
0x1B2
8
read-write
n
0x0
0x0
USB_TXCSRL11_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL11_ERROR
Error
2
3
USB_TXCSRL11_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL11_FLUSH
Flush FIFO
3
4
USB_TXCSRL11_NAKTO
NAK Timeout
7
8
USB_TXCSRL11_SETUP
Setup Packet
4
5
USB_TXCSRL11_STALL
Send STALL
4
5
USB_TXCSRL11_STALLED
Endpoint Stalled
5
6
USB_TXCSRL11_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL11_UNDRN
Underrun
2
3
TXCSRL12
USB Transmit Control and Status Endpoint 12 Low
0x1C2
8
read-write
n
0x0
0x0
USB_TXCSRL12_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL12_ERROR
Error
2
3
USB_TXCSRL12_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL12_FLUSH
Flush FIFO
3
4
USB_TXCSRL12_NAKTO
NAK Timeout
7
8
USB_TXCSRL12_SETUP
Setup Packet
4
5
USB_TXCSRL12_STALL
Send STALL
4
5
USB_TXCSRL12_STALLED
Endpoint Stalled
5
6
USB_TXCSRL12_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL12_UNDRN
Underrun
2
3
TXCSRL13
USB Transmit Control and Status Endpoint 13 Low
0x1D2
8
read-write
n
0x0
0x0
USB_TXCSRL13_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL13_ERROR
Error
2
3
USB_TXCSRL13_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL13_FLUSH
Flush FIFO
3
4
USB_TXCSRL13_NAKTO
NAK Timeout
7
8
USB_TXCSRL13_SETUP
Setup Packet
4
5
USB_TXCSRL13_STALL
Send STALL
4
5
USB_TXCSRL13_STALLED
Endpoint Stalled
5
6
USB_TXCSRL13_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL13_UNDRN
Underrun
2
3
TXCSRL14
USB Transmit Control and Status Endpoint 14 Low
0x1E2
8
read-write
n
0x0
0x0
USB_TXCSRL14_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL14_ERROR
Error
2
3
USB_TXCSRL14_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL14_FLUSH
Flush FIFO
3
4
USB_TXCSRL14_NAKTO
NAK Timeout
7
8
USB_TXCSRL14_SETUP
Setup Packet
4
5
USB_TXCSRL14_STALL
Send STALL
4
5
USB_TXCSRL14_STALLED
Endpoint Stalled
5
6
USB_TXCSRL14_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL14_UNDRN
Underrun
2
3
TXCSRL15
USB Transmit Control and Status Endpoint 15 Low
0x1F2
8
read-write
n
0x0
0x0
USB_TXCSRL15_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL15_ERROR
Error
2
3
USB_TXCSRL15_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL15_FLUSH
Flush FIFO
3
4
USB_TXCSRL15_NAKTO
NAK Timeout
7
8
USB_TXCSRL15_SETUP
Setup Packet
4
5
USB_TXCSRL15_STALL
Send STALL
4
5
USB_TXCSRL15_STALLED
Endpoint Stalled
5
6
USB_TXCSRL15_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL15_UNDRN
Underrun
2
3
TXCSRL2
USB Transmit Control and Status Endpoint 2 Low
0x122
8
read-write
n
0x0
0x0
USB_TXCSRL2_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL2_ERROR
Error
2
3
USB_TXCSRL2_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL2_FLUSH
Flush FIFO
3
4
USB_TXCSRL2_NAKTO
NAK Timeout
7
8
USB_TXCSRL2_SETUP
Setup Packet
4
5
USB_TXCSRL2_STALL
Send STALL
4
5
USB_TXCSRL2_STALLED
Endpoint Stalled
5
6
USB_TXCSRL2_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL2_UNDRN
Underrun
2
3
TXCSRL3
USB Transmit Control and Status Endpoint 3 Low
0x132
8
read-write
n
0x0
0x0
USB_TXCSRL3_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL3_ERROR
Error
2
3
USB_TXCSRL3_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL3_FLUSH
Flush FIFO
3
4
USB_TXCSRL3_NAKTO
NAK Timeout
7
8
USB_TXCSRL3_SETUP
Setup Packet
4
5
USB_TXCSRL3_STALL
Send STALL
4
5
USB_TXCSRL3_STALLED
Endpoint Stalled
5
6
USB_TXCSRL3_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL3_UNDRN
Underrun
2
3
TXCSRL4
USB Transmit Control and Status Endpoint 4 Low
0x142
8
read-write
n
0x0
0x0
USB_TXCSRL4_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL4_ERROR
Error
2
3
USB_TXCSRL4_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL4_FLUSH
Flush FIFO
3
4
USB_TXCSRL4_NAKTO
NAK Timeout
7
8
USB_TXCSRL4_SETUP
Setup Packet
4
5
USB_TXCSRL4_STALL
Send STALL
4
5
USB_TXCSRL4_STALLED
Endpoint Stalled
5
6
USB_TXCSRL4_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL4_UNDRN
Underrun
2
3
TXCSRL5
USB Transmit Control and Status Endpoint 5 Low
0x152
8
read-write
n
0x0
0x0
USB_TXCSRL5_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL5_ERROR
Error
2
3
USB_TXCSRL5_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL5_FLUSH
Flush FIFO
3
4
USB_TXCSRL5_NAKTO
NAK Timeout
7
8
USB_TXCSRL5_SETUP
Setup Packet
4
5
USB_TXCSRL5_STALL
Send STALL
4
5
USB_TXCSRL5_STALLED
Endpoint Stalled
5
6
USB_TXCSRL5_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL5_UNDRN
Underrun
2
3
TXCSRL6
USB Transmit Control and Status Endpoint 6 Low
0x162
8
read-write
n
0x0
0x0
USB_TXCSRL6_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL6_ERROR
Error
2
3
USB_TXCSRL6_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL6_FLUSH
Flush FIFO
3
4
USB_TXCSRL6_NAKTO
NAK Timeout
7
8
USB_TXCSRL6_SETUP
Setup Packet
4
5
USB_TXCSRL6_STALL
Send STALL
4
5
USB_TXCSRL6_STALLED
Endpoint Stalled
5
6
USB_TXCSRL6_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL6_UNDRN
Underrun
2
3
TXCSRL7
USB Transmit Control and Status Endpoint 7 Low
0x172
8
read-write
n
0x0
0x0
USB_TXCSRL7_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL7_ERROR
Error
2
3
USB_TXCSRL7_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL7_FLUSH
Flush FIFO
3
4
USB_TXCSRL7_NAKTO
NAK Timeout
7
8
USB_TXCSRL7_SETUP
Setup Packet
4
5
USB_TXCSRL7_STALL
Send STALL
4
5
USB_TXCSRL7_STALLED
Endpoint Stalled
5
6
USB_TXCSRL7_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL7_UNDRN
Underrun
2
3
TXCSRL8
USB Transmit Control and Status Endpoint 8 Low
0x182
8
read-write
n
0x0
0x0
USB_TXCSRL8_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL8_ERROR
Error
2
3
USB_TXCSRL8_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL8_FLUSH
Flush FIFO
3
4
USB_TXCSRL8_NAKTO
NAK Timeout
7
8
USB_TXCSRL8_SETUP
Setup Packet
4
5
USB_TXCSRL8_STALL
Send STALL
4
5
USB_TXCSRL8_STALLED
Endpoint Stalled
5
6
USB_TXCSRL8_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL8_UNDRN
Underrun
2
3
TXCSRL9
USB Transmit Control and Status Endpoint 9 Low
0x192
8
read-write
n
0x0
0x0
USB_TXCSRL9_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL9_ERROR
Error
2
3
USB_TXCSRL9_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL9_FLUSH
Flush FIFO
3
4
USB_TXCSRL9_NAKTO
NAK Timeout
7
8
USB_TXCSRL9_SETUP
Setup Packet
4
5
USB_TXCSRL9_STALL
Send STALL
4
5
USB_TXCSRL9_STALLED
Endpoint Stalled
5
6
USB_TXCSRL9_TXRDY
Transmit Packet Ready
0
1
USB_TXCSRL9_UNDRN
Underrun
2
3
TXDPKTBUFDIS
USB Transmit Double Packet Buffer Disable
0x342
16
read-write
n
0x0
0x0
USB_TXDPKTBUFDIS_EP1
EP1 TX Double-Packet Buffer Disable
1
2
USB_TXDPKTBUFDIS_EP10
EP10 TX Double-Packet Buffer Disable
10
11
USB_TXDPKTBUFDIS_EP11
EP11 TX Double-Packet Buffer Disable
11
12
USB_TXDPKTBUFDIS_EP12
EP12 TX Double-Packet Buffer Disable
12
13
USB_TXDPKTBUFDIS_EP13
EP13 TX Double-Packet Buffer Disable
13
14
USB_TXDPKTBUFDIS_EP14
EP14 TX Double-Packet Buffer Disable
14
15
USB_TXDPKTBUFDIS_EP15
EP15 TX Double-Packet Buffer Disable
15
16
USB_TXDPKTBUFDIS_EP2
EP2 TX Double-Packet Buffer Disable
2
3
USB_TXDPKTBUFDIS_EP3
EP3 TX Double-Packet Buffer Disable
3
4
USB_TXDPKTBUFDIS_EP4
EP4 TX Double-Packet Buffer Disable
4
5
USB_TXDPKTBUFDIS_EP5
EP5 TX Double-Packet Buffer Disable
5
6
USB_TXDPKTBUFDIS_EP6
EP6 TX Double-Packet Buffer Disable
6
7
USB_TXDPKTBUFDIS_EP7
EP7 TX Double-Packet Buffer Disable
7
8
USB_TXDPKTBUFDIS_EP8
EP8 TX Double-Packet Buffer Disable
8
9
USB_TXDPKTBUFDIS_EP9
EP9 TX Double-Packet Buffer Disable
9
10
TXFIFOADD
USB Transmit FIFO Start Address
0x64
16
read-write
n
0x0
0x0
USB_TXFIFOADD_ADDR
Transmit/Receive Start Address
0
9
TXFIFOSZ
USB Transmit Dynamic FIFO Sizing
0x62
8
read-write
n
0x0
0x0
USB_TXFIFOSZ_DPB
Double Packet Buffer Support
4
5
USB_TXFIFOSZ_SIZE
Max Packet Size
0
4
USB_TXFIFOSZ_SIZE_8
8
0x0
USB_TXFIFOSZ_SIZE_16
16
0x1
USB_TXFIFOSZ_SIZE_32
32
0x2
USB_TXFIFOSZ_SIZE_64
64
0x3
USB_TXFIFOSZ_SIZE_128
128
0x4
USB_TXFIFOSZ_SIZE_256
256
0x5
USB_TXFIFOSZ_SIZE_512
512
0x6
USB_TXFIFOSZ_SIZE_1024
1024
0x7
USB_TXFIFOSZ_SIZE_2048
2048
0x8
TXFUNCADDR0
USB Transmit Functional Address Endpoint 0
0x80
8
read-write
n
0x0
0x0
USB_TXFUNCADDR0_ADDR
Device Address
0
7
TXFUNCADDR1
USB Transmit Functional Address Endpoint 1
0x88
8
read-write
n
0x0
0x0
USB_TXFUNCADDR1_ADDR
Device Address
0
7
TXFUNCADDR10
USB Transmit Functional Address Endpoint 10
0xD0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR10_ADDR
Device Address
0
7
TXFUNCADDR11
USB Transmit Functional Address Endpoint 11
0xD8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR11_ADDR
Device Address
0
7
TXFUNCADDR12
USB Transmit Functional Address Endpoint 12
0xE0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR12_ADDR
Device Address
0
7
TXFUNCADDR13
USB Transmit Functional Address Endpoint 13
0xE8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR13_ADDR
Device Address
0
7
TXFUNCADDR14
USB Transmit Functional Address Endpoint 14
0xF0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR14_ADDR
Device Address
0
7
TXFUNCADDR15
USB Transmit Functional Address Endpoint 15
0xF8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR15_ADDR
Device Address
0
7
TXFUNCADDR2
USB Transmit Functional Address Endpoint 2
0x90
8
read-write
n
0x0
0x0
USB_TXFUNCADDR2_ADDR
Device Address
0
7
TXFUNCADDR3
USB Transmit Functional Address Endpoint 3
0x98
8
read-write
n
0x0
0x0
USB_TXFUNCADDR3_ADDR
Device Address
0
7
TXFUNCADDR4
USB Transmit Functional Address Endpoint 4
0xA0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR4_ADDR
Device Address
0
7
TXFUNCADDR5
USB Transmit Functional Address Endpoint 5
0xA8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR5_ADDR
Device Address
0
7
TXFUNCADDR6
USB Transmit Functional Address Endpoint 6
0xB0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR6_ADDR
Device Address
0
7
TXFUNCADDR7
USB Transmit Functional Address Endpoint 7
0xB8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR7_ADDR
Device Address
0
7
TXFUNCADDR8
USB Transmit Functional Address Endpoint 8
0xC0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR8_ADDR
Device Address
0
7
TXFUNCADDR9
USB Transmit Functional Address Endpoint 9
0xC8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR9_ADDR
Device Address
0
7
TXHUBADDR0
USB Transmit Hub Address Endpoint 0
0x82
8
read-write
n
0x0
0x0
USB_TXHUBADDR0_ADDR
Hub Address
0
7
USB_TXHUBADDR0_MULTTRAN
Multiple Translators
7
8
TXHUBADDR1
USB Transmit Hub Address Endpoint 1
0x8A
8
read-write
n
0x0
0x0
USB_TXHUBADDR1_ADDR
Hub Address
0
7
USB_TXHUBADDR1_MULTTRAN
Multiple Translators
7
8
TXHUBADDR10
USB Transmit Hub Address Endpoint 10
0xD2
8
read-write
n
0x0
0x0
USB_TXHUBADDR10_ADDR
Hub Address
0
7
USB_TXHUBADDR10_MULTTRAN
Multiple Translators
7
8
TXHUBADDR11
USB Transmit Hub Address Endpoint 11
0xDA
8
read-write
n
0x0
0x0
USB_TXHUBADDR11_ADDR
Hub Address
0
7
USB_TXHUBADDR11_MULTTRAN
Multiple Translators
7
8
TXHUBADDR12
USB Transmit Hub Address Endpoint 12
0xE2
8
read-write
n
0x0
0x0
USB_TXHUBADDR12_ADDR
Hub Address
0
7
USB_TXHUBADDR12_MULTTRAN
Multiple Translators
7
8
TXHUBADDR13
USB Transmit Hub Address Endpoint 13
0xEA
8
read-write
n
0x0
0x0
USB_TXHUBADDR13_ADDR
Hub Address
0
7
USB_TXHUBADDR13_MULTTRAN
Multiple Translators
7
8
TXHUBADDR14
USB Transmit Hub Address Endpoint 14
0xF2
8
read-write
n
0x0
0x0
USB_TXHUBADDR14_ADDR
Hub Address
0
7
USB_TXHUBADDR14_MULTTRAN
Multiple Translators
7
8
TXHUBADDR15
USB Transmit Hub Address Endpoint 15
0xFA
8
read-write
n
0x0
0x0
USB_TXHUBADDR15_ADDR
Hub Address
0
7
USB_TXHUBADDR15_MULTTRAN
Multiple Translators
7
8
TXHUBADDR2
USB Transmit Hub Address Endpoint 2
0x92
8
read-write
n
0x0
0x0
USB_TXHUBADDR2_ADDR
Hub Address
0
7
USB_TXHUBADDR2_MULTTRAN
Multiple Translators
7
8
TXHUBADDR3
USB Transmit Hub Address Endpoint 3
0x9A
8
read-write
n
0x0
0x0
USB_TXHUBADDR3_ADDR
Hub Address
0
7
USB_TXHUBADDR3_MULTTRAN
Multiple Translators
7
8
TXHUBADDR4
USB Transmit Hub Address Endpoint 4
0xA2
8
read-write
n
0x0
0x0
USB_TXHUBADDR4_ADDR
Hub Address
0
7
USB_TXHUBADDR4_MULTTRAN
Multiple Translators
7
8
TXHUBADDR5
USB Transmit Hub Address Endpoint 5
0xAA
8
read-write
n
0x0
0x0
USB_TXHUBADDR5_ADDR
Hub Address
0
7
USB_TXHUBADDR5_MULTTRAN
Multiple Translators
7
8
TXHUBADDR6
USB Transmit Hub Address Endpoint 6
0xB2
8
read-write
n
0x0
0x0
USB_TXHUBADDR6_ADDR
Hub Address
0
7
USB_TXHUBADDR6_MULTTRAN
Multiple Translators
7
8
TXHUBADDR7
USB Transmit Hub Address Endpoint 7
0xBA
8
read-write
n
0x0
0x0
USB_TXHUBADDR7_ADDR
Hub Address
0
7
USB_TXHUBADDR7_MULTTRAN
Multiple Translators
7
8
TXHUBADDR8
USB Transmit Hub Address Endpoint 8
0xC2
8
read-write
n
0x0
0x0
USB_TXHUBADDR8_ADDR
Hub Address
0
7
USB_TXHUBADDR8_MULTTRAN
Multiple Translators
7
8
TXHUBADDR9
USB Transmit Hub Address Endpoint 9
0xCA
8
read-write
n
0x0
0x0
USB_TXHUBADDR9_ADDR
Hub Address
0
7
USB_TXHUBADDR9_MULTTRAN
Multiple Translators
7
8
TXHUBPORT0
USB Transmit Hub Port Endpoint 0
0x83
8
read-write
n
0x0
0x0
USB_TXHUBPORT0_PORT
Hub Port
0
7
TXHUBPORT1
USB Transmit Hub Port Endpoint 1
0x8B
8
read-write
n
0x0
0x0
USB_TXHUBPORT1_PORT
Hub Port
0
7
TXHUBPORT10
USB Transmit Hub Port Endpoint 10
0xD3
8
read-write
n
0x0
0x0
USB_TXHUBPORT10_PORT
Hub Port
0
7
TXHUBPORT11
USB Transmit Hub Port Endpoint 11
0xDB
8
read-write
n
0x0
0x0
USB_TXHUBPORT11_PORT
Hub Port
0
7
TXHUBPORT12
USB Transmit Hub Port Endpoint 12
0xE3
8
read-write
n
0x0
0x0
USB_TXHUBPORT12_PORT
Hub Port
0
7
TXHUBPORT13
USB Transmit Hub Port Endpoint 13
0xEB
8
read-write
n
0x0
0x0
USB_TXHUBPORT13_PORT
Hub Port
0
7
TXHUBPORT14
USB Transmit Hub Port Endpoint 14
0xF3
8
read-write
n
0x0
0x0
USB_TXHUBPORT14_PORT
Hub Port
0
7
TXHUBPORT15
USB Transmit Hub Port Endpoint 15
0xFB
8
read-write
n
0x0
0x0
USB_TXHUBPORT15_PORT
Hub Port
0
7
TXHUBPORT2
USB Transmit Hub Port Endpoint 2
0x93
8
read-write
n
0x0
0x0
USB_TXHUBPORT2_PORT
Hub Port
0
7
TXHUBPORT3
USB Transmit Hub Port Endpoint 3
0x9B
8
read-write
n
0x0
0x0
USB_TXHUBPORT3_PORT
Hub Port
0
7
TXHUBPORT4
USB Transmit Hub Port Endpoint 4
0xA3
8
read-write
n
0x0
0x0
USB_TXHUBPORT4_PORT
Hub Port
0
7
TXHUBPORT5
USB Transmit Hub Port Endpoint 5
0xAB
8
read-write
n
0x0
0x0
USB_TXHUBPORT5_PORT
Hub Port
0
7
TXHUBPORT6
USB Transmit Hub Port Endpoint 6
0xB3
8
read-write
n
0x0
0x0
USB_TXHUBPORT6_PORT
Hub Port
0
7
TXHUBPORT7
USB Transmit Hub Port Endpoint 7
0xBB
8
read-write
n
0x0
0x0
USB_TXHUBPORT7_PORT
Hub Port
0
7
TXHUBPORT8
USB Transmit Hub Port Endpoint 8
0xC3
8
read-write
n
0x0
0x0
USB_TXHUBPORT8_PORT
Hub Port
0
7
TXHUBPORT9
USB Transmit Hub Port Endpoint 9
0xCB
8
read-write
n
0x0
0x0
USB_TXHUBPORT9_PORT
Hub Port
0
7
TXIE
USB Transmit Interrupt Enable
0x6
16
read-write
n
0x0
0x0
USB_TXIE_EP0
TX and RX Endpoint 0 Interrupt Enable
0
1
USB_TXIE_EP1
TX Endpoint 1 Interrupt Enable
1
2
USB_TXIE_EP10
TX Endpoint 10 Interrupt Enable
10
11
USB_TXIE_EP11
TX Endpoint 11 Interrupt Enable
11
12
USB_TXIE_EP12
TX Endpoint 12 Interrupt Enable
12
13
USB_TXIE_EP13
TX Endpoint 13 Interrupt Enable
13
14
USB_TXIE_EP14
TX Endpoint 14 Interrupt Enable
14
15
USB_TXIE_EP15
TX Endpoint 15 Interrupt Enable
15
16
USB_TXIE_EP2
TX Endpoint 2 Interrupt Enable
2
3
USB_TXIE_EP3
TX Endpoint 3 Interrupt Enable
3
4
USB_TXIE_EP4
TX Endpoint 4 Interrupt Enable
4
5
USB_TXIE_EP5
TX Endpoint 5 Interrupt Enable
5
6
USB_TXIE_EP6
TX Endpoint 6 Interrupt Enable
6
7
USB_TXIE_EP7
TX Endpoint 7 Interrupt Enable
7
8
USB_TXIE_EP8
TX Endpoint 8 Interrupt Enable
8
9
USB_TXIE_EP9
TX Endpoint 9 Interrupt Enable
9
10
TXINTERVAL1
USB Host Transmit Interval Endpoint 1
0x11B
8
read-write
n
0x0
0x0
USB_TXINTERVAL1_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL1_TXPOLL
TX Polling
0
8
TXINTERVAL10
USB Host Transmit Interval Endpoint 10
0x1AB
8
read-write
n
0x0
0x0
USB_TXINTERVAL10_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL10_TXPOLL
TX Polling
0
8
TXINTERVAL11
USB Host Transmit Interval Endpoint 11
0x1BB
8
read-write
n
0x0
0x0
USB_TXINTERVAL11_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL11_TXPOLL
TX Polling
0
8
TXINTERVAL12
USB Host Transmit Interval Endpoint 12
0x1CB
8
read-write
n
0x0
0x0
USB_TXINTERVAL12_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL12_TXPOLL
TX Polling
0
8
TXINTERVAL13
USB Host Transmit Interval Endpoint 13
0x1DB
8
read-write
n
0x0
0x0
USB_TXINTERVAL13_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL13_TXPOLL
TX Polling
0
8
TXINTERVAL14
USB Host Transmit Interval Endpoint 14
0x1EB
8
read-write
n
0x0
0x0
USB_TXINTERVAL14_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL14_TXPOLL
TX Polling
0
8
TXINTERVAL15
USB Host Transmit Interval Endpoint 15
0x1FB
8
read-write
n
0x0
0x0
USB_TXINTERVAL15_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL15_TXPOLL
TX Polling
0
8
TXINTERVAL2
USB Host Transmit Interval Endpoint 2
0x12B
8
read-write
n
0x0
0x0
USB_TXINTERVAL2_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL2_TXPOLL
TX Polling
0
8
TXINTERVAL3
USB Host Transmit Interval Endpoint 3
0x13B
8
read-write
n
0x0
0x0
USB_TXINTERVAL3_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL3_TXPOLL
TX Polling
0
8
TXINTERVAL4
USB Host Transmit Interval Endpoint 4
0x14B
8
read-write
n
0x0
0x0
USB_TXINTERVAL4_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL4_TXPOLL
TX Polling
0
8
TXINTERVAL5
USB Host Transmit Interval Endpoint 5
0x15B
8
read-write
n
0x0
0x0
USB_TXINTERVAL5_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL5_TXPOLL
TX Polling
0
8
TXINTERVAL6
USB Host Transmit Interval Endpoint 6
0x16B
8
read-write
n
0x0
0x0
USB_TXINTERVAL6_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL6_TXPOLL
TX Polling
0
8
TXINTERVAL7
USB Host Transmit Interval Endpoint 7
0x17B
8
read-write
n
0x0
0x0
USB_TXINTERVAL7_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL7_TXPOLL
TX Polling
0
8
TXINTERVAL8
USB Host Transmit Interval Endpoint 8
0x18B
8
read-write
n
0x0
0x0
USB_TXINTERVAL8_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL8_TXPOLL
TX Polling
0
8
TXINTERVAL9
USB Host Transmit Interval Endpoint 9
0x19B
8
read-write
n
0x0
0x0
USB_TXINTERVAL9_NAKLMT
NAK Limit
0
8
USB_TXINTERVAL9_TXPOLL
TX Polling
0
8
TXIS
USB Transmit Interrupt Status
0x2
16
read-write
n
0x0
0x0
USB_TXIS_EP0
TX and RX Endpoint 0 Interrupt
0
1
USB_TXIS_EP1
TX Endpoint 1 Interrupt
1
2
USB_TXIS_EP10
TX Endpoint 10 Interrupt
10
11
USB_TXIS_EP11
TX Endpoint 11 Interrupt
11
12
USB_TXIS_EP12
TX Endpoint 12 Interrupt
12
13
USB_TXIS_EP13
TX Endpoint 13 Interrupt
13
14
USB_TXIS_EP14
TX Endpoint 14 Interrupt
14
15
USB_TXIS_EP15
TX Endpoint 15 Interrupt
15
16
USB_TXIS_EP2
TX Endpoint 2 Interrupt
2
3
USB_TXIS_EP3
TX Endpoint 3 Interrupt
3
4
USB_TXIS_EP4
TX Endpoint 4 Interrupt
4
5
USB_TXIS_EP5
TX Endpoint 5 Interrupt
5
6
USB_TXIS_EP6
TX Endpoint 6 Interrupt
6
7
USB_TXIS_EP7
TX Endpoint 7 Interrupt
7
8
USB_TXIS_EP8
TX Endpoint 8 Interrupt
8
9
USB_TXIS_EP9
TX Endpoint 9 Interrupt
9
10
TXMAXP1
USB Maximum Transmit Data Endpoint 1
0x110
16
read-write
n
0x0
0x0
USB_TXMAXP1_MAXLOAD
Maximum Payload
0
11
TXMAXP10
USB Maximum Transmit Data Endpoint 10
0x1A0
16
read-write
n
0x0
0x0
USB_TXMAXP10_MAXLOAD
Maximum Payload
0
11
TXMAXP11
USB Maximum Transmit Data Endpoint 11
0x1B0
16
read-write
n
0x0
0x0
USB_TXMAXP11_MAXLOAD
Maximum Payload
0
11
TXMAXP12
USB Maximum Transmit Data Endpoint 12
0x1C0
16
read-write
n
0x0
0x0
USB_TXMAXP12_MAXLOAD
Maximum Payload
0
11
TXMAXP13
USB Maximum Transmit Data Endpoint 13
0x1D0
16
read-write
n
0x0
0x0
USB_TXMAXP13_MAXLOAD
Maximum Payload
0
11
TXMAXP14
USB Maximum Transmit Data Endpoint 14
0x1E0
16
read-write
n
0x0
0x0
USB_TXMAXP14_MAXLOAD
Maximum Payload
0
11
TXMAXP15
USB Maximum Transmit Data Endpoint 15
0x1F0
16
read-write
n
0x0
0x0
USB_TXMAXP15_MAXLOAD
Maximum Payload
0
11
TXMAXP2
USB Maximum Transmit Data Endpoint 2
0x120
16
read-write
n
0x0
0x0
USB_TXMAXP2_MAXLOAD
Maximum Payload
0
11
TXMAXP3
USB Maximum Transmit Data Endpoint 3
0x130
16
read-write
n
0x0
0x0
USB_TXMAXP3_MAXLOAD
Maximum Payload
0
11
TXMAXP4
USB Maximum Transmit Data Endpoint 4
0x140
16
read-write
n
0x0
0x0
USB_TXMAXP4_MAXLOAD
Maximum Payload
0
11
TXMAXP5
USB Maximum Transmit Data Endpoint 5
0x150
16
read-write
n
0x0
0x0
USB_TXMAXP5_MAXLOAD
Maximum Payload
0
11
TXMAXP6
USB Maximum Transmit Data Endpoint 6
0x160
16
read-write
n
0x0
0x0
USB_TXMAXP6_MAXLOAD
Maximum Payload
0
11
TXMAXP7
USB Maximum Transmit Data Endpoint 7
0x170
16
read-write
n
0x0
0x0
USB_TXMAXP7_MAXLOAD
Maximum Payload
0
11
TXMAXP8
USB Maximum Transmit Data Endpoint 8
0x180
16
read-write
n
0x0
0x0
USB_TXMAXP8_MAXLOAD
Maximum Payload
0
11
TXMAXP9
USB Maximum Transmit Data Endpoint 9
0x190
16
read-write
n
0x0
0x0
USB_TXMAXP9_MAXLOAD
Maximum Payload
0
11
TXTYPE1
USB Host Transmit Configure Type Endpoint 1
0x11A
8
read-write
n
0x0
0x0
USB_TXTYPE1_PROTO
Protocol
4
6
USB_TXTYPE1_PROTO_CTRL
Control
0x0
USB_TXTYPE1_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE1_PROTO_BULK
Bulk
0x2
USB_TXTYPE1_PROTO_INT
Interrupt
0x3
USB_TXTYPE1_SPEED
Operating Speed
6
8
USB_TXTYPE1_SPEED_DFLT
Default
0x0
USB_TXTYPE1_SPEED_FULL
Full
0x2
USB_TXTYPE1_SPEED_LOW
Low
0x3
USB_TXTYPE1_TEP
Target Endpoint Number
0
4
TXTYPE10
USB Host Transmit Configure Type Endpoint 10
0x1AA
8
read-write
n
0x0
0x0
USB_TXTYPE10_PROTO
Protocol
4
6
USB_TXTYPE10_PROTO_CTRL
Control
0x0
USB_TXTYPE10_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE10_PROTO_BULK
Bulk
0x2
USB_TXTYPE10_PROTO_INT
Interrupt
0x3
USB_TXTYPE10_SPEED
Operating Speed
6
8
USB_TXTYPE10_SPEED_DFLT
Default
0x0
USB_TXTYPE10_SPEED_FULL
Full
0x2
USB_TXTYPE10_SPEED_LOW
Low
0x3
USB_TXTYPE10_TEP
Target Endpoint Number
0
4
TXTYPE11
USB Host Transmit Configure Type Endpoint 11
0x1BA
8
read-write
n
0x0
0x0
USB_TXTYPE11_PROTO
Protocol
4
6
USB_TXTYPE11_PROTO_CTRL
Control
0x0
USB_TXTYPE11_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE11_PROTO_BULK
Bulk
0x2
USB_TXTYPE11_PROTO_INT
Interrupt
0x3
USB_TXTYPE11_SPEED
Operating Speed
6
8
USB_TXTYPE11_SPEED_DFLT
Default
0x0
USB_TXTYPE11_SPEED_FULL
Full
0x2
USB_TXTYPE11_SPEED_LOW
Low
0x3
USB_TXTYPE11_TEP
Target Endpoint Number
0
4
TXTYPE12
USB Host Transmit Configure Type Endpoint 12
0x1CA
8
read-write
n
0x0
0x0
USB_TXTYPE12_PROTO
Protocol
4
6
USB_TXTYPE12_PROTO_CTRL
Control
0x0
USB_TXTYPE12_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE12_PROTO_BULK
Bulk
0x2
USB_TXTYPE12_PROTO_INT
Interrupt
0x3
USB_TXTYPE12_SPEED
Operating Speed
6
8
USB_TXTYPE12_SPEED_DFLT
Default
0x0
USB_TXTYPE12_SPEED_FULL
Full
0x2
USB_TXTYPE12_SPEED_LOW
Low
0x3
USB_TXTYPE12_TEP
Target Endpoint Number
0
4
TXTYPE13
USB Host Transmit Configure Type Endpoint 13
0x1DA
8
read-write
n
0x0
0x0
USB_TXTYPE13_PROTO
Protocol
4
6
USB_TXTYPE13_PROTO_CTRL
Control
0x0
USB_TXTYPE13_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE13_PROTO_BULK
Bulk
0x2
USB_TXTYPE13_PROTO_INT
Interrupt
0x3
USB_TXTYPE13_SPEED
Operating Speed
6
8
USB_TXTYPE13_SPEED_DFLT
Default
0x0
USB_TXTYPE13_SPEED_FULL
Full
0x2
USB_TXTYPE13_SPEED_LOW
Low
0x3
USB_TXTYPE13_TEP
Target Endpoint Number
0
4
TXTYPE14
USB Host Transmit Configure Type Endpoint 14
0x1EA
8
read-write
n
0x0
0x0
USB_TXTYPE14_PROTO
Protocol
4
6
USB_TXTYPE14_PROTO_CTRL
Control
0x0
USB_TXTYPE14_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE14_PROTO_BULK
Bulk
0x2
USB_TXTYPE14_PROTO_INT
Interrupt
0x3
USB_TXTYPE14_SPEED
Operating Speed
6
8
USB_TXTYPE14_SPEED_DFLT
Default
0x0
USB_TXTYPE14_SPEED_FULL
Full
0x2
USB_TXTYPE14_SPEED_LOW
Low
0x3
USB_TXTYPE14_TEP
Target Endpoint Number
0
4
TXTYPE15
USB Host Transmit Configure Type Endpoint 15
0x1FA
8
read-write
n
0x0
0x0
USB_TXTYPE15_PROTO
Protocol
4
6
USB_TXTYPE15_PROTO_CTRL
Control
0x0
USB_TXTYPE15_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE15_PROTO_BULK
Bulk
0x2
USB_TXTYPE15_PROTO_INT
Interrupt
0x3
USB_TXTYPE15_SPEED
Operating Speed
6
8
USB_TXTYPE15_SPEED_DFLT
Default
0x0
USB_TXTYPE15_SPEED_FULL
Full
0x2
USB_TXTYPE15_SPEED_LOW
Low
0x3
USB_TXTYPE15_TEP
Target Endpoint Number
0
4
TXTYPE2
USB Host Transmit Configure Type Endpoint 2
0x12A
8
read-write
n
0x0
0x0
USB_TXTYPE2_PROTO
Protocol
4
6
USB_TXTYPE2_PROTO_CTRL
Control
0x0
USB_TXTYPE2_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE2_PROTO_BULK
Bulk
0x2
USB_TXTYPE2_PROTO_INT
Interrupt
0x3
USB_TXTYPE2_SPEED
Operating Speed
6
8
USB_TXTYPE2_SPEED_DFLT
Default
0x0
USB_TXTYPE2_SPEED_FULL
Full
0x2
USB_TXTYPE2_SPEED_LOW
Low
0x3
USB_TXTYPE2_TEP
Target Endpoint Number
0
4
TXTYPE3
USB Host Transmit Configure Type Endpoint 3
0x13A
8
read-write
n
0x0
0x0
USB_TXTYPE3_PROTO
Protocol
4
6
USB_TXTYPE3_PROTO_CTRL
Control
0x0
USB_TXTYPE3_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE3_PROTO_BULK
Bulk
0x2
USB_TXTYPE3_PROTO_INT
Interrupt
0x3
USB_TXTYPE3_SPEED
Operating Speed
6
8
USB_TXTYPE3_SPEED_DFLT
Default
0x0
USB_TXTYPE3_SPEED_FULL
Full
0x2
USB_TXTYPE3_SPEED_LOW
Low
0x3
USB_TXTYPE3_TEP
Target Endpoint Number
0
4
TXTYPE4
USB Host Transmit Configure Type Endpoint 4
0x14A
8
read-write
n
0x0
0x0
USB_TXTYPE4_PROTO
Protocol
4
6
USB_TXTYPE4_PROTO_CTRL
Control
0x0
USB_TXTYPE4_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE4_PROTO_BULK
Bulk
0x2
USB_TXTYPE4_PROTO_INT
Interrupt
0x3
USB_TXTYPE4_SPEED
Operating Speed
6
8
USB_TXTYPE4_SPEED_DFLT
Default
0x0
USB_TXTYPE4_SPEED_FULL
Full
0x2
USB_TXTYPE4_SPEED_LOW
Low
0x3
USB_TXTYPE4_TEP
Target Endpoint Number
0
4
TXTYPE5
USB Host Transmit Configure Type Endpoint 5
0x15A
8
read-write
n
0x0
0x0
USB_TXTYPE5_PROTO
Protocol
4
6
USB_TXTYPE5_PROTO_CTRL
Control
0x0
USB_TXTYPE5_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE5_PROTO_BULK
Bulk
0x2
USB_TXTYPE5_PROTO_INT
Interrupt
0x3
USB_TXTYPE5_SPEED
Operating Speed
6
8
USB_TXTYPE5_SPEED_DFLT
Default
0x0
USB_TXTYPE5_SPEED_FULL
Full
0x2
USB_TXTYPE5_SPEED_LOW
Low
0x3
USB_TXTYPE5_TEP
Target Endpoint Number
0
4
TXTYPE6
USB Host Transmit Configure Type Endpoint 6
0x16A
8
read-write
n
0x0
0x0
USB_TXTYPE6_PROTO
Protocol
4
6
USB_TXTYPE6_PROTO_CTRL
Control
0x0
USB_TXTYPE6_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE6_PROTO_BULK
Bulk
0x2
USB_TXTYPE6_PROTO_INT
Interrupt
0x3
USB_TXTYPE6_SPEED
Operating Speed
6
8
USB_TXTYPE6_SPEED_DFLT
Default
0x0
USB_TXTYPE6_SPEED_FULL
Full
0x2
USB_TXTYPE6_SPEED_LOW
Low
0x3
USB_TXTYPE6_TEP
Target Endpoint Number
0
4
TXTYPE7
USB Host Transmit Configure Type Endpoint 7
0x17A
8
read-write
n
0x0
0x0
USB_TXTYPE7_PROTO
Protocol
4
6
USB_TXTYPE7_PROTO_CTRL
Control
0x0
USB_TXTYPE7_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE7_PROTO_BULK
Bulk
0x2
USB_TXTYPE7_PROTO_INT
Interrupt
0x3
USB_TXTYPE7_SPEED
Operating Speed
6
8
USB_TXTYPE7_SPEED_DFLT
Default
0x0
USB_TXTYPE7_SPEED_FULL
Full
0x2
USB_TXTYPE7_SPEED_LOW
Low
0x3
USB_TXTYPE7_TEP
Target Endpoint Number
0
4
TXTYPE8
USB Host Transmit Configure Type Endpoint 8
0x18A
8
read-write
n
0x0
0x0
USB_TXTYPE8_PROTO
Protocol
4
6
USB_TXTYPE8_PROTO_CTRL
Control
0x0
USB_TXTYPE8_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE8_PROTO_BULK
Bulk
0x2
USB_TXTYPE8_PROTO_INT
Interrupt
0x3
USB_TXTYPE8_SPEED
Operating Speed
6
8
USB_TXTYPE8_SPEED_DFLT
Default
0x0
USB_TXTYPE8_SPEED_FULL
Full
0x2
USB_TXTYPE8_SPEED_LOW
Low
0x3
USB_TXTYPE8_TEP
Target Endpoint Number
0
4
TXTYPE9
USB Host Transmit Configure Type Endpoint 9
0x19A
8
read-write
n
0x0
0x0
USB_TXTYPE9_PROTO
Protocol
4
6
USB_TXTYPE9_PROTO_CTRL
Control
0x0
USB_TXTYPE9_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE9_PROTO_BULK
Bulk
0x2
USB_TXTYPE9_PROTO_INT
Interrupt
0x3
USB_TXTYPE9_SPEED
Operating Speed
6
8
USB_TXTYPE9_SPEED_DFLT
Default
0x0
USB_TXTYPE9_SPEED_FULL
Full
0x2
USB_TXTYPE9_SPEED_LOW
Low
0x3
USB_TXTYPE9_TEP
Target Endpoint Number
0
4
TYPE0
USB Type Endpoint 0
0x10A
8
read-write
n
0x0
0x0
USB_TYPE0_SPEED
Operating Speed
6
8
USB_TYPE0_SPEED_FULL
Full
0x2
USB_TYPE0_SPEED_LOW
Low
0x3
USB0CONTIM
USB Connect Timing
0x7A
8
read-write
n
0x0
0x0
USB_CONTIM_WTCON
Connect Wait
4
8
USB_CONTIM_WTID
Wait ID
0
4
USB0COUNT0
USB Receive Byte Count Endpoint 0
0x108
8
read-write
n
0x0
0x0
USB_COUNT0_COUNT
FIFO Count
0
7
USB0CSRH0
USB Control and Status Endpoint 0 High
0x103
8
write-only
n
0x0
0x0
USB_CSRH0_DT
Data Toggle
1
2
write-only
USB_CSRH0_DTWE
Data Toggle Write Enable
2
3
write-only
USB_CSRH0_FLUSH
Flush FIFO
0
1
write-only
USB0CSRL0
USB Control and Status Endpoint 0 Low
0x102
8
write-only
n
0x0
0x0
USB_CSRL0_DATAEND
Data End
3
4
write-only
USB_CSRL0_RXRDY
Receive Packet Ready
0
1
write-only
USB_CSRL0_RXRDYC
RXRDY Clear
6
7
write-only
USB_CSRL0_SETEND
Setup End
4
5
write-only
USB_CSRL0_SETENDC
Setup End Clear
7
8
write-only
USB_CSRL0_STALL
Send Stall
5
6
write-only
USB_CSRL0_STALLED
Endpoint Stalled
2
3
write-only
USB_CSRL0_TXRDY
Transmit Packet Ready
1
2
write-only
USB0DEVCTL
USB Device Control
0x60
8
read-write
n
0x0
0x0
USB_DEVCTL_DEV
Device Mode
7
8
USB_DEVCTL_FSDEV
Full-Speed Device Detected
6
7
USB_DEVCTL_HOST
Host Mode
2
3
USB_DEVCTL_HOSTREQ
Host Request
1
2
USB_DEVCTL_LSDEV
Low-Speed Device Detected
5
6
USB_DEVCTL_SESSION
Session Start/End
0
1
USB_DEVCTL_VBUS
VBUS Level
3
5
USB_DEVCTL_VBUS_NONE
Below SessionEnd
0x0
USB_DEVCTL_VBUS_SEND
Above SessionEnd, below AValid
0x1
USB_DEVCTL_VBUS_AVALID
Above AValid, below VBUSValid
0x2
USB_DEVCTL_VBUS_VALID
Above VBUSValid
0x3
USB0DMASEL
USB DMA Select
0x450
read-write
n
0x0
0x0
USB_DMASEL_DMAARX
DMA A RX Select
0
4
USB_DMASEL_DMAATX
DMA A TX Select
4
8
USB_DMASEL_DMABRX
DMA B RX Select
8
12
USB_DMASEL_DMABTX
DMA B TX Select
12
16
USB_DMASEL_DMACRX
DMA C RX Select
16
20
USB_DMASEL_DMACTX
DMA C TX Select
20
24
USB0DRIM
USB Device RESUME Interrupt Mask
0x414
read-write
n
0x0
0x0
USB_DRIM_RESUME
RESUME Interrupt Mask
0
1
USB0DRISC
USB Device RESUME Interrupt Status and Clear
0x418
write-only
n
0x0
0x0
USB_DRISC_RESUME
RESUME Interrupt Status and Clear
0
1
write-only
USB0DRRIS
USB Device RESUME Raw Interrupt Status
0x410
read-write
n
0x0
0x0
USB_DRRIS_RESUME
RESUME Interrupt Status
0
1
USB0EPC
USB External Power Control
0x400
read-write
n
0x0
0x0
USB_EPC_EPEN
External Power Supply Enable Configuration
0
2
USB_EPC_EPEN_LOW
Power Enable Active Low
0x0
USB_EPC_EPEN_HIGH
Power Enable Active High
0x1
USB_EPC_EPEN_VBLOW
Power Enable High if VBUS Low
0x2
USB_EPC_EPEN_VBHIGH
Power Enable High if VBUS High
0x3
USB_EPC_EPENDE
EPEN Drive Enable
2
3
USB_EPC_PFLTACT
Power Fault Action
8
10
USB_EPC_PFLTACT_UNCHG
Unchanged
0x0
USB_EPC_PFLTACT_TRIS
Tristate
0x1
USB_EPC_PFLTACT_LOW
Low
0x2
USB_EPC_PFLTACT_HIGH
High
0x3
USB_EPC_PFLTAEN
Power Fault Action Enable
6
7
USB_EPC_PFLTEN
Power Fault Input Enable
4
5
USB_EPC_PFLTSEN_HIGH
Power Fault Sense
5
6
USB0EPCIM
USB External Power Control Interrupt Mask
0x408
read-write
n
0x0
0x0
USB_EPCIM_PF
USB Power Fault Interrupt Mask
0
1
USB0EPCISC
USB External Power Control Interrupt Status and Clear
0x40C
read-write
n
0x0
0x0
USB_EPCISC_PF
USB Power Fault Interrupt Status and Clear
0
1
USB0EPCRIS
USB External Power Control Raw Interrupt Status
0x404
read-write
n
0x0
0x0
USB_EPCRIS_PF
USB Power Fault Interrupt Status
0
1
USB0EPIDX
USB Endpoint Index
0xE
8
read-write
n
0x0
0x0
USB_EPIDX_EPIDX
Endpoint Index
0
4
USB0FADDR
USB Device Functional Address
0x0
8
read-write
n
0x0
0x0
USB_FADDR
Function Address
0
7
USB0FIFO0
USB FIFO Endpoint 0
0x20
read-write
n
0x0
0x0
USB_FIFO0_EPDATA
Endpoint Data
0
32
USB0FIFO1
USB FIFO Endpoint 1
0x24
read-write
n
0x0
0x0
USB_FIFO1_EPDATA
Endpoint Data
0
32
USB0FIFO10
USB FIFO Endpoint 10
0x48
read-write
n
0x0
0x0
USB_FIFO10_EPDATA
Endpoint Data
0
32
USB0FIFO11
USB FIFO Endpoint 11
0x4C
read-write
n
0x0
0x0
USB_FIFO11_EPDATA
Endpoint Data
0
32
USB0FIFO12
USB FIFO Endpoint 12
0x50
read-write
n
0x0
0x0
USB_FIFO12_EPDATA
Endpoint Data
0
32
USB0FIFO13
USB FIFO Endpoint 13
0x54
read-write
n
0x0
0x0
USB_FIFO13_EPDATA
Endpoint Data
0
32
USB0FIFO14
USB FIFO Endpoint 14
0x58
read-write
n
0x0
0x0
USB_FIFO14_EPDATA
Endpoint Data
0
32
USB0FIFO15
USB FIFO Endpoint 15
0x5C
read-write
n
0x0
0x0
USB_FIFO15_EPDATA
Endpoint Data
0
32
USB0FIFO2
USB FIFO Endpoint 2
0x28
read-write
n
0x0
0x0
USB_FIFO2_EPDATA
Endpoint Data
0
32
USB0FIFO3
USB FIFO Endpoint 3
0x2C
read-write
n
0x0
0x0
USB_FIFO3_EPDATA
Endpoint Data
0
32
USB0FIFO4
USB FIFO Endpoint 4
0x30
read-write
n
0x0
0x0
USB_FIFO4_EPDATA
Endpoint Data
0
32
USB0FIFO5
USB FIFO Endpoint 5
0x34
read-write
n
0x0
0x0
USB_FIFO5_EPDATA
Endpoint Data
0
32
USB0FIFO6
USB FIFO Endpoint 6
0x38
read-write
n
0x0
0x0
USB_FIFO6_EPDATA
Endpoint Data
0
32
USB0FIFO7
USB FIFO Endpoint 7
0x3C
read-write
n
0x0
0x0
USB_FIFO7_EPDATA
Endpoint Data
0
32
USB0FIFO8
USB FIFO Endpoint 8
0x40
read-write
n
0x0
0x0
USB_FIFO8_EPDATA
Endpoint Data
0
32
USB0FIFO9
USB FIFO Endpoint 9
0x44
read-write
n
0x0
0x0
USB_FIFO9_EPDATA
Endpoint Data
0
32
USB0FRAME
USB Frame Value
0xC
16
read-write
n
0x0
0x0
USB_FRAME
Frame Number
0
11
USB0FSEOF
USB Full-Speed Last Transaction to End of Frame Timing
0x7D
8
read-write
n
0x0
0x0
USB_FSEOF_FSEOFG
Full-Speed End-of-Frame Gap
0
8
USB0GPCS
USB General-Purpose Control and Status
0x41C
read-write
n
0x0
0x0
USB_GPCS_DEVMOD
Device Mode
0
1
USB_GPCS_DEVMODOTG
Enable Device Mode
1
2
USB0IDVIM
USB ID Valid Detect Interrupt Mask
0x448
read-write
n
0x0
0x0
USB_IDVIM_ID
ID Valid Detect Interrupt Mask
0
1
USB0IDVISC
USB ID Valid Detect Interrupt Status and Clear
0x44C
read-write
n
0x0
0x0
USB_IDVISC_ID
ID Valid Detect Interrupt Status and Clear
0
1
USB0IDVRIS
USB ID Valid Detect Raw Interrupt Status
0x444
read-write
n
0x0
0x0
USB_IDVRIS_ID
ID Valid Detect Raw Interrupt Status
0
1
USB0IE
USB Interrupt Enable
0xB
8
read-write
n
0x0
0x0
USB_IE_BABBLE
Enable Babble Interrupt
2
3
USB_IE_CONN
Enable Connect Interrupt
4
5
USB_IE_DISCON
Enable Disconnect Interrupt
5
6
USB_IE_RESUME
Enable RESUME Interrupt
1
2
USB_IE_SESREQ
Enable Session Request
6
7
USB_IE_SOF
Enable Start-of-Frame Interrupt
3
4
USB_IE_SUSPND
Enable SUSPEND Interrupt
0
1
USB_IE_VBUSERR
Enable VBUS Error Interrupt
7
8
USB0IS
USB General Interrupt Status
0xA
8
read-write
n
0x0
0x0
USB_IS_BABBLE
Babble Detected
2
3
USB_IS_CONN
Session Connect
4
5
USB_IS_DISCON
Session Disconnect
5
6
USB_IS_RESUME
RESUME Signaling Detected
1
2
USB_IS_SESREQ
SESSION REQUEST
6
7
USB_IS_SOF
Start of Frame
3
4
USB_IS_SUSPEND
SUSPEND Signaling Detected
0
1
USB_IS_VBUSERR
VBUS Error
7
8
USB0LSEOF
USB Low-Speed Last Transaction to End of Frame Timing
0x7E
8
read-write
n
0x0
0x0
USB_LSEOF_LSEOFG
Low-Speed End-of-Frame Gap
0
8
USB0NAKLMT
USB NAK Limit
0x10B
8
read-write
n
0x0
0x0
USB_NAKLMT_NAKLMT
EP0 NAK Limit
0
5
USB0POWER
USB Power
0x1
8
read-write
n
0x0
0x0
USB_POWER_ISOUP
Isochronous Update
7
8
USB_POWER_PWRDNPHY
Power Down PHY
0
1
USB_POWER_RESET
RESET Signaling
3
4
USB_POWER_RESUME
RESUME Signaling
2
3
USB_POWER_SOFTCONN
Soft Connect/Disconnect
6
7
USB_POWER_SUSPEND
SUSPEND Mode
1
2
USB0RQPKTCOUNT1
USB Request Packet Count in Block Transfer Endpoint 1
0x304
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT1
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT10
USB Request Packet Count in Block Transfer Endpoint 10
0x328
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT10_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT11
USB Request Packet Count in Block Transfer Endpoint 11
0x32C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT11_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT12
USB Request Packet Count in Block Transfer Endpoint 12
0x330
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT12_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT13
USB Request Packet Count in Block Transfer Endpoint 13
0x334
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT13_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT14
USB Request Packet Count in Block Transfer Endpoint 14
0x338
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT14_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT15
USB Request Packet Count in Block Transfer Endpoint 15
0x33C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT15_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT2
USB Request Packet Count in Block Transfer Endpoint 2
0x308
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT2
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT3
USB Request Packet Count in Block Transfer Endpoint 3
0x30C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT3
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT4
USB Request Packet Count in Block Transfer Endpoint 4
0x310
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT4_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT5
USB Request Packet Count in Block Transfer Endpoint 5
0x314
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT5_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT6
USB Request Packet Count in Block Transfer Endpoint 6
0x318
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT6_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT7
USB Request Packet Count in Block Transfer Endpoint 7
0x31C
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT7_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT8
USB Request Packet Count in Block Transfer Endpoint 8
0x320
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT8_COUNT
Block Transfer Packet Count
0
16
USB0RQPKTCOUNT9
USB Request Packet Count in Block Transfer Endpoint 9
0x324
16
read-write
n
0x0
0x0
USB_RQPKTCOUNT9_COUNT
Block Transfer Packet Count
0
16
USB0RXCOUNT1
USB Receive Byte Count Endpoint 1
0x118
16
read-write
n
0x0
0x0
USB_RXCOUNT1_COUNT
Receive Packet Count
0
13
USB0RXCOUNT10
USB Receive Byte Count Endpoint 10
0x1A8
16
read-write
n
0x0
0x0
USB_RXCOUNT10_COUNT
Receive Packet Count
0
13
USB0RXCOUNT11
USB Receive Byte Count Endpoint 11
0x1B8
16
read-write
n
0x0
0x0
USB_RXCOUNT11_COUNT
Receive Packet Count
0
13
USB0RXCOUNT12
USB Receive Byte Count Endpoint 12
0x1C8
16
read-write
n
0x0
0x0
USB_RXCOUNT12_COUNT
Receive Packet Count
0
13
USB0RXCOUNT13
USB Receive Byte Count Endpoint 13
0x1D8
16
read-write
n
0x0
0x0
USB_RXCOUNT13_COUNT
Receive Packet Count
0
13
USB0RXCOUNT14
USB Receive Byte Count Endpoint 14
0x1E8
16
read-write
n
0x0
0x0
USB_RXCOUNT14_COUNT
Receive Packet Count
0
13
USB0RXCOUNT15
USB Receive Byte Count Endpoint 15
0x1F8
16
read-write
n
0x0
0x0
USB_RXCOUNT15_COUNT
Receive Packet Count
0
13
USB0RXCOUNT2
USB Receive Byte Count Endpoint 2
0x128
16
read-write
n
0x0
0x0
USB_RXCOUNT2_COUNT
Receive Packet Count
0
13
USB0RXCOUNT3
USB Receive Byte Count Endpoint 3
0x138
16
read-write
n
0x0
0x0
USB_RXCOUNT3_COUNT
Receive Packet Count
0
13
USB0RXCOUNT4
USB Receive Byte Count Endpoint 4
0x148
16
read-write
n
0x0
0x0
USB_RXCOUNT4_COUNT
Receive Packet Count
0
13
USB0RXCOUNT5
USB Receive Byte Count Endpoint 5
0x158
16
read-write
n
0x0
0x0
USB_RXCOUNT5_COUNT
Receive Packet Count
0
13
USB0RXCOUNT6
USB Receive Byte Count Endpoint 6
0x168
16
read-write
n
0x0
0x0
USB_RXCOUNT6_COUNT
Receive Packet Count
0
13
USB0RXCOUNT7
USB Receive Byte Count Endpoint 7
0x178
16
read-write
n
0x0
0x0
USB_RXCOUNT7_COUNT
Receive Packet Count
0
13
USB0RXCOUNT8
USB Receive Byte Count Endpoint 8
0x188
16
read-write
n
0x0
0x0
USB_RXCOUNT8_COUNT
Receive Packet Count
0
13
USB0RXCOUNT9
USB Receive Byte Count Endpoint 9
0x198
16
read-write
n
0x0
0x0
USB_RXCOUNT9_COUNT
Receive Packet Count
0
13
USB0RXCSRH1
USB Receive Control and Status Endpoint 1 High
0x117
8
read-write
n
0x0
0x0
USB_RXCSRH1_AUTOCL
Auto Clear
7
8
USB_RXCSRH1_AUTORQ
Auto Request
6
7
USB_RXCSRH1_DMAEN
DMA Request Enable
5
6
USB_RXCSRH1_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH1_DT
Data Toggle
1
2
USB_RXCSRH1_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH1_PIDERR
PID Error
4
5
USB0RXCSRH10
USB Receive Control and Status Endpoint 10 High
0x1A7
8
read-write
n
0x0
0x0
USB_RXCSRH10_AUTOCL
Auto Clear
7
8
USB_RXCSRH10_AUTORQ
Auto Request
6
7
USB_RXCSRH10_DMAEN
DMA Request Enable
5
6
USB_RXCSRH10_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH10_DT
Data Toggle
1
2
USB_RXCSRH10_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH10_PIDERR
PID Error
4
5
USB0RXCSRH11
USB Receive Control and Status Endpoint 11 High
0x1B7
8
read-write
n
0x0
0x0
USB_RXCSRH11_AUTOCL
Auto Clear
7
8
USB_RXCSRH11_AUTORQ
Auto Request
6
7
USB_RXCSRH11_DMAEN
DMA Request Enable
5
6
USB_RXCSRH11_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH11_DT
Data Toggle
1
2
USB_RXCSRH11_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH11_PIDERR
PID Error
4
5
USB0RXCSRH12
USB Receive Control and Status Endpoint 12 High
0x1C7
8
read-write
n
0x0
0x0
USB_RXCSRH12_AUTOCL
Auto Clear
7
8
USB_RXCSRH12_AUTORQ
Auto Request
6
7
USB_RXCSRH12_DMAEN
DMA Request Enable
5
6
USB_RXCSRH12_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH12_DT
Data Toggle
1
2
USB_RXCSRH12_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH12_PIDERR
PID Error
4
5
USB0RXCSRH13
USB Receive Control and Status Endpoint 13 High
0x1D7
8
read-write
n
0x0
0x0
USB_RXCSRH13_AUTOCL
Auto Clear
7
8
USB_RXCSRH13_AUTORQ
Auto Request
6
7
USB_RXCSRH13_DMAEN
DMA Request Enable
5
6
USB_RXCSRH13_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH13_DT
Data Toggle
1
2
USB_RXCSRH13_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH13_PIDERR
PID Error
4
5
USB0RXCSRH14
USB Receive Control and Status Endpoint 14 High
0x1E7
8
read-write
n
0x0
0x0
USB_RXCSRH14_AUTOCL
Auto Clear
7
8
USB_RXCSRH14_AUTORQ
Auto Request
6
7
USB_RXCSRH14_DMAEN
DMA Request Enable
5
6
USB_RXCSRH14_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH14_DT
Data Toggle
1
2
USB_RXCSRH14_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH14_PIDERR
PID Error
4
5
USB0RXCSRH15
USB Receive Control and Status Endpoint 15 High
0x1F7
8
read-write
n
0x0
0x0
USB_RXCSRH15_AUTOCL
Auto Clear
7
8
USB_RXCSRH15_AUTORQ
Auto Request
6
7
USB_RXCSRH15_DMAEN
DMA Request Enable
5
6
USB_RXCSRH15_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH15_DT
Data Toggle
1
2
USB_RXCSRH15_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH15_PIDERR
PID Error
4
5
USB0RXCSRH2
USB Receive Control and Status Endpoint 2 High
0x127
8
read-write
n
0x0
0x0
USB_RXCSRH2_AUTOCL
Auto Clear
7
8
USB_RXCSRH2_AUTORQ
Auto Request
6
7
USB_RXCSRH2_DMAEN
DMA Request Enable
5
6
USB_RXCSRH2_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH2_DT
Data Toggle
1
2
USB_RXCSRH2_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH2_PIDERR
PID Error
4
5
USB0RXCSRH3
USB Receive Control and Status Endpoint 3 High
0x137
8
read-write
n
0x0
0x0
USB_RXCSRH3_AUTOCL
Auto Clear
7
8
USB_RXCSRH3_AUTORQ
Auto Request
6
7
USB_RXCSRH3_DMAEN
DMA Request Enable
5
6
USB_RXCSRH3_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH3_DT
Data Toggle
1
2
USB_RXCSRH3_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH3_PIDERR
PID Error
4
5
USB0RXCSRH4
USB Receive Control and Status Endpoint 4 High
0x147
8
read-write
n
0x0
0x0
USB_RXCSRH4_AUTOCL
Auto Clear
7
8
USB_RXCSRH4_AUTORQ
Auto Request
6
7
USB_RXCSRH4_DMAEN
DMA Request Enable
5
6
USB_RXCSRH4_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH4_DT
Data Toggle
1
2
USB_RXCSRH4_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH4_PIDERR
PID Error
4
5
USB0RXCSRH5
USB Receive Control and Status Endpoint 5 High
0x157
8
read-write
n
0x0
0x0
USB_RXCSRH5_AUTOCL
Auto Clear
7
8
USB_RXCSRH5_AUTORQ
Auto Request
6
7
USB_RXCSRH5_DMAEN
DMA Request Enable
5
6
USB_RXCSRH5_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH5_DT
Data Toggle
1
2
USB_RXCSRH5_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH5_PIDERR
PID Error
4
5
USB0RXCSRH6
USB Receive Control and Status Endpoint 6 High
0x167
8
read-write
n
0x0
0x0
USB_RXCSRH6_AUTOCL
Auto Clear
7
8
USB_RXCSRH6_AUTORQ
Auto Request
6
7
USB_RXCSRH6_DMAEN
DMA Request Enable
5
6
USB_RXCSRH6_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH6_DT
Data Toggle
1
2
USB_RXCSRH6_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH6_PIDERR
PID Error
4
5
USB0RXCSRH7
USB Receive Control and Status Endpoint 7 High
0x177
8
read-write
n
0x0
0x0
USB_RXCSRH7_AUTOCL
Auto Clear
7
8
USB_RXCSRH7_AUTORQ
Auto Request
6
7
USB_RXCSRH7_DMAEN
DMA Request Enable
5
6
USB_RXCSRH7_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH7_DT
Data Toggle
1
2
USB_RXCSRH7_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH7_PIDERR
PID Error
4
5
USB0RXCSRH8
USB Receive Control and Status Endpoint 8 High
0x187
8
read-write
n
0x0
0x0
USB_RXCSRH8_AUTOCL
Auto Clear
7
8
USB_RXCSRH8_AUTORQ
Auto Request
6
7
USB_RXCSRH8_DMAEN
DMA Request Enable
5
6
USB_RXCSRH8_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH8_DT
Data Toggle
1
2
USB_RXCSRH8_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH8_PIDERR
PID Error
4
5
USB0RXCSRH9
USB Receive Control and Status Endpoint 9 High
0x197
8
read-write
n
0x0
0x0
USB_RXCSRH9_AUTOCL
Auto Clear
7
8
USB_RXCSRH9_AUTORQ
Auto Request
6
7
USB_RXCSRH9_DMAEN
DMA Request Enable
5
6
USB_RXCSRH9_DMAMOD
DMA Request Mode
3
4
USB_RXCSRH9_DT
Data Toggle
1
2
USB_RXCSRH9_DTWE
Data Toggle Write Enable
2
3
USB_RXCSRH9_PIDERR
PID Error
4
5
USB0RXCSRL1
USB Receive Control and Status Endpoint 1 Low
0x116
8
read-write
n
0x0
0x0
USB_RXCSRL1_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL1_DATAERR
Data Error
3
4
USB_RXCSRL1_FLUSH
Flush FIFO
4
5
USB_RXCSRL1_FULL
FIFO Full
1
2
USB_RXCSRL1_OVER
Overrun
2
3
USB_RXCSRL1_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL1_STALL
Send STALL
5
6
USB_RXCSRL1_STALLED
Endpoint Stalled
6
7
USB0RXCSRL10
USB Receive Control and Status Endpoint 10 Low
0x1A6
8
read-write
n
0x0
0x0
USB_RXCSRL10_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL10_DATAERR
Data Error
3
4
USB_RXCSRL10_FLUSH
Flush FIFO
4
5
USB_RXCSRL10_FULL
FIFO Full
1
2
USB_RXCSRL10_OVER
Overrun
2
3
USB_RXCSRL10_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL10_STALL
Send STALL
5
6
USB_RXCSRL10_STALLED
Endpoint Stalled
6
7
USB0RXCSRL11
USB Receive Control and Status Endpoint 11 Low
0x1B6
8
read-write
n
0x0
0x0
USB_RXCSRL11_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL11_DATAERR
Data Error
3
4
USB_RXCSRL11_FLUSH
Flush FIFO
4
5
USB_RXCSRL11_FULL
FIFO Full
1
2
USB_RXCSRL11_OVER
Overrun
2
3
USB_RXCSRL11_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL11_STALL
Send STALL
5
6
USB_RXCSRL11_STALLED
Endpoint Stalled
6
7
USB0RXCSRL12
USB Receive Control and Status Endpoint 12 Low
0x1C6
8
read-write
n
0x0
0x0
USB_RXCSRL12_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL12_DATAERR
Data Error
3
4
USB_RXCSRL12_FLUSH
Flush FIFO
4
5
USB_RXCSRL12_FULL
FIFO Full
1
2
USB_RXCSRL12_OVER
Overrun
2
3
USB_RXCSRL12_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL12_STALL
Send STALL
5
6
USB_RXCSRL12_STALLED
Endpoint Stalled
6
7
USB0RXCSRL13
USB Receive Control and Status Endpoint 13 Low
0x1D6
8
read-write
n
0x0
0x0
USB_RXCSRL13_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL13_DATAERR
Data Error
3
4
USB_RXCSRL13_FLUSH
Flush FIFO
4
5
USB_RXCSRL13_FULL
FIFO Full
1
2
USB_RXCSRL13_OVER
Overrun
2
3
USB_RXCSRL13_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL13_STALL
Send STALL
5
6
USB_RXCSRL13_STALLED
Endpoint Stalled
6
7
USB0RXCSRL14
USB Receive Control and Status Endpoint 14 Low
0x1E6
8
read-write
n
0x0
0x0
USB_RXCSRL14_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL14_DATAERR
Data Error
3
4
USB_RXCSRL14_FLUSH
Flush FIFO
4
5
USB_RXCSRL14_FULL
FIFO Full
1
2
USB_RXCSRL14_OVER
Overrun
2
3
USB_RXCSRL14_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL14_STALL
Send STALL
5
6
USB_RXCSRL14_STALLED
Endpoint Stalled
6
7
USB0RXCSRL15
USB Receive Control and Status Endpoint 15 Low
0x1F6
8
read-write
n
0x0
0x0
USB_RXCSRL15_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL15_DATAERR
Data Error
3
4
USB_RXCSRL15_FLUSH
Flush FIFO
4
5
USB_RXCSRL15_FULL
FIFO Full
1
2
USB_RXCSRL15_OVER
Overrun
2
3
USB_RXCSRL15_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL15_STALL
Send STALL
5
6
USB_RXCSRL15_STALLED
Endpoint Stalled
6
7
USB0RXCSRL2
USB Receive Control and Status Endpoint 2 Low
0x126
8
read-write
n
0x0
0x0
USB_RXCSRL2_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL2_DATAERR
Data Error
3
4
USB_RXCSRL2_FLUSH
Flush FIFO
4
5
USB_RXCSRL2_FULL
FIFO Full
1
2
USB_RXCSRL2_OVER
Overrun
2
3
USB_RXCSRL2_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL2_STALL
Send STALL
5
6
USB_RXCSRL2_STALLED
Endpoint Stalled
6
7
USB0RXCSRL3
USB Receive Control and Status Endpoint 3 Low
0x136
8
read-write
n
0x0
0x0
USB_RXCSRL3_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL3_DATAERR
Data Error
3
4
USB_RXCSRL3_FLUSH
Flush FIFO
4
5
USB_RXCSRL3_FULL
FIFO Full
1
2
USB_RXCSRL3_OVER
Overrun
2
3
USB_RXCSRL3_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL3_STALL
Send STALL
5
6
USB_RXCSRL3_STALLED
Endpoint Stalled
6
7
USB0RXCSRL4
USB Receive Control and Status Endpoint 4 Low
0x146
8
read-write
n
0x0
0x0
USB_RXCSRL4_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL4_DATAERR
Data Error
3
4
USB_RXCSRL4_FLUSH
Flush FIFO
4
5
USB_RXCSRL4_FULL
FIFO Full
1
2
USB_RXCSRL4_OVER
Overrun
2
3
USB_RXCSRL4_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL4_STALL
Send STALL
5
6
USB_RXCSRL4_STALLED
Endpoint Stalled
6
7
USB0RXCSRL5
USB Receive Control and Status Endpoint 5 Low
0x156
8
read-write
n
0x0
0x0
USB_RXCSRL5_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL5_DATAERR
Data Error
3
4
USB_RXCSRL5_FLUSH
Flush FIFO
4
5
USB_RXCSRL5_FULL
FIFO Full
1
2
USB_RXCSRL5_OVER
Overrun
2
3
USB_RXCSRL5_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL5_STALL
Send STALL
5
6
USB_RXCSRL5_STALLED
Endpoint Stalled
6
7
USB0RXCSRL6
USB Receive Control and Status Endpoint 6 Low
0x166
8
read-write
n
0x0
0x0
USB_RXCSRL6_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL6_DATAERR
Data Error
3
4
USB_RXCSRL6_FLUSH
Flush FIFO
4
5
USB_RXCSRL6_FULL
FIFO Full
1
2
USB_RXCSRL6_OVER
Overrun
2
3
USB_RXCSRL6_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL6_STALL
Send STALL
5
6
USB_RXCSRL6_STALLED
Endpoint Stalled
6
7
USB0RXCSRL7
USB Receive Control and Status Endpoint 7 Low
0x176
8
read-write
n
0x0
0x0
USB_RXCSRL7_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL7_DATAERR
Data Error
3
4
USB_RXCSRL7_FLUSH
Flush FIFO
4
5
USB_RXCSRL7_FULL
FIFO Full
1
2
USB_RXCSRL7_OVER
Overrun
2
3
USB_RXCSRL7_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL7_STALL
Send STALL
5
6
USB_RXCSRL7_STALLED
Endpoint Stalled
6
7
USB0RXCSRL8
USB Receive Control and Status Endpoint 8 Low
0x186
8
read-write
n
0x0
0x0
USB_RXCSRL8_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL8_DATAERR
Data Error
3
4
USB_RXCSRL8_FLUSH
Flush FIFO
4
5
USB_RXCSRL8_FULL
FIFO Full
1
2
USB_RXCSRL8_OVER
Overrun
2
3
USB_RXCSRL8_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL8_STALL
Send STALL
5
6
USB_RXCSRL8_STALLED
Endpoint Stalled
6
7
USB0RXCSRL9
USB Receive Control and Status Endpoint 9 Low
0x196
8
read-write
n
0x0
0x0
USB_RXCSRL9_CLRDT
Clear Data Toggle
7
8
USB_RXCSRL9_DATAERR
Data Error
3
4
USB_RXCSRL9_FLUSH
Flush FIFO
4
5
USB_RXCSRL9_FULL
FIFO Full
1
2
USB_RXCSRL9_OVER
Overrun
2
3
USB_RXCSRL9_RXRDY
Receive Packet Ready
0
1
USB_RXCSRL9_STALL
Send STALL
5
6
USB_RXCSRL9_STALLED
Endpoint Stalled
6
7
USB0RXDPKTBUFDIS
USB Receive Double Packet Buffer Disable
0x340
16
read-write
n
0x0
0x0
USB_RXDPKTBUFDIS_EP1
EP1 RX Double-Packet Buffer Disable
1
2
USB_RXDPKTBUFDIS_EP10
EP10 RX Double-Packet Buffer Disable
10
11
USB_RXDPKTBUFDIS_EP11
EP11 RX Double-Packet Buffer Disable
11
12
USB_RXDPKTBUFDIS_EP12
EP12 RX Double-Packet Buffer Disable
12
13
USB_RXDPKTBUFDIS_EP13
EP13 RX Double-Packet Buffer Disable
13
14
USB_RXDPKTBUFDIS_EP14
EP14 RX Double-Packet Buffer Disable
14
15
USB_RXDPKTBUFDIS_EP15
EP15 RX Double-Packet Buffer Disable
15
16
USB_RXDPKTBUFDIS_EP2
EP2 RX Double-Packet Buffer Disable
2
3
USB_RXDPKTBUFDIS_EP3
EP3 RX Double-Packet Buffer Disable
3
4
USB_RXDPKTBUFDIS_EP4
EP4 RX Double-Packet Buffer Disable
4
5
USB_RXDPKTBUFDIS_EP5
EP5 RX Double-Packet Buffer Disable
5
6
USB_RXDPKTBUFDIS_EP6
EP6 RX Double-Packet Buffer Disable
6
7
USB_RXDPKTBUFDIS_EP7
EP7 RX Double-Packet Buffer Disable
7
8
USB_RXDPKTBUFDIS_EP8
EP8 RX Double-Packet Buffer Disable
8
9
USB_RXDPKTBUFDIS_EP9
EP9 RX Double-Packet Buffer Disable
9
10
USB0RXFIFOADD
USB Receive FIFO Start Address
0x66
16
read-write
n
0x0
0x0
USB_RXFIFOADD_ADDR
Transmit/Receive Start Address
0
9
USB0RXFIFOSZ
USB Receive Dynamic FIFO Sizing
0x63
8
read-write
n
0x0
0x0
USB_RXFIFOSZ_DPB
Double Packet Buffer Support
4
5
USB_RXFIFOSZ_SIZE
Max Packet Size
0
4
USB_RXFIFOSZ_SIZE_8
8
0x0
USB_RXFIFOSZ_SIZE_16
16
0x1
USB_RXFIFOSZ_SIZE_32
32
0x2
USB_RXFIFOSZ_SIZE_64
64
0x3
USB_RXFIFOSZ_SIZE_128
128
0x4
USB_RXFIFOSZ_SIZE_256
256
0x5
USB_RXFIFOSZ_SIZE_512
512
0x6
USB_RXFIFOSZ_SIZE_1024
1024
0x7
USB_RXFIFOSZ_SIZE_2048
2048
0x8
USB0RXFUNCADDR1
USB Receive Functional Address Endpoint 1
0x8C
8
read-write
n
0x0
0x0
USB_RXFUNCADDR1_ADDR
Device Address
0
7
USB0RXFUNCADDR10
USB Receive Functional Address Endpoint 10
0xD4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR10_ADDR
Device Address
0
7
USB0RXFUNCADDR11
USB Receive Functional Address Endpoint 11
0xDC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR11_ADDR
Device Address
0
7
USB0RXFUNCADDR12
USB Receive Functional Address Endpoint 12
0xE4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR12_ADDR
Device Address
0
7
USB0RXFUNCADDR13
USB Receive Functional Address Endpoint 13
0xEC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR13_ADDR
Device Address
0
7
USB0RXFUNCADDR14
USB Receive Functional Address Endpoint 14
0xF4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR14_ADDR
Device Address
0
7
USB0RXFUNCADDR15
USB Receive Functional Address Endpoint 15
0xFC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR15_ADDR
Device Address
0
7
USB0RXFUNCADDR2
USB Receive Functional Address Endpoint 2
0x94
8
read-write
n
0x0
0x0
USB_RXFUNCADDR2_ADDR
Device Address
0
7
USB0RXFUNCADDR3
USB Receive Functional Address Endpoint 3
0x9C
8
read-write
n
0x0
0x0
USB_RXFUNCADDR3_ADDR
Device Address
0
7
USB0RXFUNCADDR4
USB Receive Functional Address Endpoint 4
0xA4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR4_ADDR
Device Address
0
7
USB0RXFUNCADDR5
USB Receive Functional Address Endpoint 5
0xAC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR5_ADDR
Device Address
0
7
USB0RXFUNCADDR6
USB Receive Functional Address Endpoint 6
0xB4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR6_ADDR
Device Address
0
7
USB0RXFUNCADDR7
USB Receive Functional Address Endpoint 7
0xBC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR7_ADDR
Device Address
0
7
USB0RXFUNCADDR8
USB Receive Functional Address Endpoint 8
0xC4
8
read-write
n
0x0
0x0
USB_RXFUNCADDR8_ADDR
Device Address
0
7
USB0RXFUNCADDR9
USB Receive Functional Address Endpoint 9
0xCC
8
read-write
n
0x0
0x0
USB_RXFUNCADDR9_ADDR
Device Address
0
7
USB0RXHUBADDR1
USB Receive Hub Address Endpoint 1
0x8E
8
read-write
n
0x0
0x0
USB_RXHUBADDR1_ADDR
Hub Address
0
7
USB_RXHUBADDR1_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR10
USB Receive Hub Address Endpoint 10
0xD6
8
read-write
n
0x0
0x0
USB_RXHUBADDR10_ADDR
Hub Address
0
7
USB_RXHUBADDR10_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR11
USB Receive Hub Address Endpoint 11
0xDE
8
read-write
n
0x0
0x0
USB_RXHUBADDR11_ADDR
Hub Address
0
7
USB_RXHUBADDR11_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR12
USB Receive Hub Address Endpoint 12
0xE6
8
read-write
n
0x0
0x0
USB_RXHUBADDR12_ADDR
Hub Address
0
7
USB_RXHUBADDR12_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR13
USB Receive Hub Address Endpoint 13
0xEE
8
read-write
n
0x0
0x0
USB_RXHUBADDR13_ADDR
Hub Address
0
7
USB_RXHUBADDR13_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR14
USB Receive Hub Address Endpoint 14
0xF6
8
read-write
n
0x0
0x0
USB_RXHUBADDR14_ADDR
Hub Address
0
7
USB_RXHUBADDR14_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR15
USB Receive Hub Address Endpoint 15
0xFE
8
read-write
n
0x0
0x0
USB_RXHUBADDR15_ADDR
Hub Address
0
7
USB_RXHUBADDR15_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR2
USB Receive Hub Address Endpoint 2
0x96
8
read-write
n
0x0
0x0
USB_RXHUBADDR2_ADDR
Hub Address
0
7
USB_RXHUBADDR2_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR3
USB Receive Hub Address Endpoint 3
0x9E
8
read-write
n
0x0
0x0
USB_RXHUBADDR3_ADDR
Hub Address
0
7
USB_RXHUBADDR3_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR4
USB Receive Hub Address Endpoint 4
0xA6
8
read-write
n
0x0
0x0
USB_RXHUBADDR4_ADDR
Hub Address
0
7
USB_RXHUBADDR4_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR5
USB Receive Hub Address Endpoint 5
0xAE
8
read-write
n
0x0
0x0
USB_RXHUBADDR5_ADDR
Hub Address
0
7
USB_RXHUBADDR5_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR6
USB Receive Hub Address Endpoint 6
0xB6
8
read-write
n
0x0
0x0
USB_RXHUBADDR6_ADDR
Hub Address
0
7
USB_RXHUBADDR6_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR7
USB Receive Hub Address Endpoint 7
0xBE
8
read-write
n
0x0
0x0
USB_RXHUBADDR7_ADDR
Hub Address
0
7
USB_RXHUBADDR7_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR8
USB Receive Hub Address Endpoint 8
0xC6
8
read-write
n
0x0
0x0
USB_RXHUBADDR8_ADDR
Hub Address
0
7
USB_RXHUBADDR8_MULTTRAN
Multiple Translators
7
8
USB0RXHUBADDR9
USB Receive Hub Address Endpoint 9
0xCE
8
read-write
n
0x0
0x0
USB_RXHUBADDR9_ADDR
Hub Address
0
7
USB_RXHUBADDR9_MULTTRAN
Multiple Translators
7
8
USB0RXHUBPORT1
USB Receive Hub Port Endpoint 1
0x8F
8
read-write
n
0x0
0x0
USB_RXHUBPORT1_PORT
Hub Port
0
7
USB0RXHUBPORT10
USB Receive Hub Port Endpoint 10
0xD7
8
read-write
n
0x0
0x0
USB_RXHUBPORT10_PORT
Hub Port
0
7
USB0RXHUBPORT11
USB Receive Hub Port Endpoint 11
0xDF
8
read-write
n
0x0
0x0
USB_RXHUBPORT11_PORT
Hub Port
0
7
USB0RXHUBPORT12
USB Receive Hub Port Endpoint 12
0xE7
8
read-write
n
0x0
0x0
USB_RXHUBPORT12_PORT
Hub Port
0
7
USB0RXHUBPORT13
USB Receive Hub Port Endpoint 13
0xEF
8
read-write
n
0x0
0x0
USB_RXHUBPORT13_PORT
Hub Port
0
7
USB0RXHUBPORT14
USB Receive Hub Port Endpoint 14
0xF7
8
read-write
n
0x0
0x0
USB_RXHUBPORT14_PORT
Hub Port
0
7
USB0RXHUBPORT15
USB Receive Hub Port Endpoint 15
0xFF
8
read-write
n
0x0
0x0
USB_RXHUBPORT15_PORT
Hub Port
0
7
USB0RXHUBPORT2
USB Receive Hub Port Endpoint 2
0x97
8
read-write
n
0x0
0x0
USB_RXHUBPORT2_PORT
Hub Port
0
7
USB0RXHUBPORT3
USB Receive Hub Port Endpoint 3
0x9F
8
read-write
n
0x0
0x0
USB_RXHUBPORT3_PORT
Hub Port
0
7
USB0RXHUBPORT4
USB Receive Hub Port Endpoint 4
0xA7
8
read-write
n
0x0
0x0
USB_RXHUBPORT4_PORT
Hub Port
0
7
USB0RXHUBPORT5
USB Receive Hub Port Endpoint 5
0xAF
8
read-write
n
0x0
0x0
USB_RXHUBPORT5_PORT
Hub Port
0
7
USB0RXHUBPORT6
USB Receive Hub Port Endpoint 6
0xB7
8
read-write
n
0x0
0x0
USB_RXHUBPORT6_PORT
Hub Port
0
7
USB0RXHUBPORT7
USB Receive Hub Port Endpoint 7
0xBF
8
read-write
n
0x0
0x0
USB_RXHUBPORT7_PORT
Hub Port
0
7
USB0RXHUBPORT8
USB Receive Hub Port Endpoint 8
0xC7
8
read-write
n
0x0
0x0
USB_RXHUBPORT8_PORT
Hub Port
0
7
USB0RXHUBPORT9
USB Receive Hub Port Endpoint 9
0xCF
8
read-write
n
0x0
0x0
USB_RXHUBPORT9_PORT
Hub Port
0
7
USB0RXIE
USB Receive Interrupt Enable
0x8
16
read-write
n
0x0
0x0
USB_RXIE_EP1
RX Endpoint 1 Interrupt Enable
1
2
USB_RXIE_EP10
RX Endpoint 10 Interrupt Enable
10
11
USB_RXIE_EP11
RX Endpoint 11 Interrupt Enable
11
12
USB_RXIE_EP12
RX Endpoint 12 Interrupt Enable
12
13
USB_RXIE_EP13
RX Endpoint 13 Interrupt Enable
13
14
USB_RXIE_EP14
RX Endpoint 14 Interrupt Enable
14
15
USB_RXIE_EP15
RX Endpoint 15 Interrupt Enable
15
16
USB_RXIE_EP2
RX Endpoint 2 Interrupt Enable
2
3
USB_RXIE_EP3
RX Endpoint 3 Interrupt Enable
3
4
USB_RXIE_EP4
RX Endpoint 4 Interrupt Enable
4
5
USB_RXIE_EP5
RX Endpoint 5 Interrupt Enable
5
6
USB_RXIE_EP6
RX Endpoint 6 Interrupt Enable
6
7
USB_RXIE_EP7
RX Endpoint 7 Interrupt Enable
7
8
USB_RXIE_EP8
RX Endpoint 8 Interrupt Enable
8
9
USB_RXIE_EP9
RX Endpoint 9 Interrupt Enable
9
10
USB0RXINTERVAL1
USB Host Receive Polling Interval Endpoint 1
0x11D
8
read-write
n
0x0
0x0
USB_RXINTERVAL1_TXPOLL
RX Polling
0
8
USB0RXINTERVAL10
USB Host Receive Polling Interval Endpoint 10
0x1AD
8
read-write
n
0x0
0x0
USB_RXINTERVAL10_TXPOLL
RX Polling
0
8
USB0RXINTERVAL11
USB Host Receive Polling Interval Endpoint 11
0x1BD
8
read-write
n
0x0
0x0
USB_RXINTERVAL11_TXPOLL
RX Polling
0
8
USB0RXINTERVAL12
USB Host Receive Polling Interval Endpoint 12
0x1CD
8
read-write
n
0x0
0x0
USB_RXINTERVAL12_TXPOLL
RX Polling
0
8
USB0RXINTERVAL13
USB Host Receive Polling Interval Endpoint 13
0x1DD
8
read-write
n
0x0
0x0
USB_RXINTERVAL13_TXPOLL
RX Polling
0
8
USB0RXINTERVAL14
USB Host Receive Polling Interval Endpoint 14
0x1ED
8
read-write
n
0x0
0x0
USB_RXINTERVAL14_TXPOLL
RX Polling
0
8
USB0RXINTERVAL15
USB Host Receive Polling Interval Endpoint 15
0x1FD
8
read-write
n
0x0
0x0
USB_RXINTERVAL15_TXPOLL
RX Polling
0
8
USB0RXINTERVAL2
USB Host Receive Polling Interval Endpoint 2
0x12D
8
read-write
n
0x0
0x0
USB_RXINTERVAL2_TXPOLL
RX Polling
0
8
USB0RXINTERVAL3
USB Host Receive Polling Interval Endpoint 3
0x13D
8
read-write
n
0x0
0x0
USB_RXINTERVAL3_TXPOLL
RX Polling
0
8
USB0RXINTERVAL4
USB Host Receive Polling Interval Endpoint 4
0x14D
8
read-write
n
0x0
0x0
USB_RXINTERVAL4_TXPOLL
RX Polling
0
8
USB0RXINTERVAL5
USB Host Receive Polling Interval Endpoint 5
0x15D
8
read-write
n
0x0
0x0
USB_RXINTERVAL5_TXPOLL
RX Polling
0
8
USB0RXINTERVAL6
USB Host Receive Polling Interval Endpoint 6
0x16D
8
read-write
n
0x0
0x0
USB_RXINTERVAL6_TXPOLL
RX Polling
0
8
USB0RXINTERVAL7
USB Host Receive Polling Interval Endpoint 7
0x17D
8
read-write
n
0x0
0x0
USB_RXINTERVAL7_TXPOLL
RX Polling
0
8
USB0RXINTERVAL8
USB Host Receive Polling Interval Endpoint 8
0x18D
8
read-write
n
0x0
0x0
USB_RXINTERVAL8_TXPOLL
RX Polling
0
8
USB0RXINTERVAL9
USB Host Receive Polling Interval Endpoint 9
0x19D
8
read-write
n
0x0
0x0
USB_RXINTERVAL9_TXPOLL
RX Polling
0
8
USB0RXIS
USB Receive Interrupt Status
0x4
16
read-write
n
0x0
0x0
USB_RXIS_EP1
RX Endpoint 1 Interrupt
1
2
USB_RXIS_EP10
RX Endpoint 10 Interrupt
10
11
USB_RXIS_EP11
RX Endpoint 11 Interrupt
11
12
USB_RXIS_EP12
RX Endpoint 12 Interrupt
12
13
USB_RXIS_EP13
RX Endpoint 13 Interrupt
13
14
USB_RXIS_EP14
RX Endpoint 14 Interrupt
14
15
USB_RXIS_EP15
RX Endpoint 15 Interrupt
15
16
USB_RXIS_EP2
RX Endpoint 2 Interrupt
2
3
USB_RXIS_EP3
RX Endpoint 3 Interrupt
3
4
USB_RXIS_EP4
RX Endpoint 4 Interrupt
4
5
USB_RXIS_EP5
RX Endpoint 5 Interrupt
5
6
USB_RXIS_EP6
RX Endpoint 6 Interrupt
6
7
USB_RXIS_EP7
RX Endpoint 7 Interrupt
7
8
USB_RXIS_EP8
RX Endpoint 8 Interrupt
8
9
USB_RXIS_EP9
RX Endpoint 9 Interrupt
9
10
USB0RXMAXP1
USB Maximum Receive Data Endpoint 1
0x114
16
read-write
n
0x0
0x0
USB_RXMAXP1_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP10
USB Maximum Receive Data Endpoint 10
0x1A4
16
read-write
n
0x0
0x0
USB_RXMAXP10_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP11
USB Maximum Receive Data Endpoint 11
0x1B4
16
read-write
n
0x0
0x0
USB_RXMAXP11_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP12
USB Maximum Receive Data Endpoint 12
0x1C4
16
read-write
n
0x0
0x0
USB_RXMAXP12_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP13
USB Maximum Receive Data Endpoint 13
0x1D4
16
read-write
n
0x0
0x0
USB_RXMAXP13_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP14
USB Maximum Receive Data Endpoint 14
0x1E4
16
read-write
n
0x0
0x0
USB_RXMAXP14_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP15
USB Maximum Receive Data Endpoint 15
0x1F4
16
read-write
n
0x0
0x0
USB_RXMAXP15_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP2
USB Maximum Receive Data Endpoint 2
0x124
16
read-write
n
0x0
0x0
USB_RXMAXP2_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP3
USB Maximum Receive Data Endpoint 3
0x134
16
read-write
n
0x0
0x0
USB_RXMAXP3_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP4
USB Maximum Receive Data Endpoint 4
0x144
16
read-write
n
0x0
0x0
USB_RXMAXP4_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP5
USB Maximum Receive Data Endpoint 5
0x154
16
read-write
n
0x0
0x0
USB_RXMAXP5_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP6
USB Maximum Receive Data Endpoint 6
0x164
16
read-write
n
0x0
0x0
USB_RXMAXP6_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP7
USB Maximum Receive Data Endpoint 7
0x174
16
read-write
n
0x0
0x0
USB_RXMAXP7_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP8
USB Maximum Receive Data Endpoint 8
0x184
16
read-write
n
0x0
0x0
USB_RXMAXP8_MAXLOAD
Maximum Payload
0
11
USB0RXMAXP9
USB Maximum Receive Data Endpoint 9
0x194
16
read-write
n
0x0
0x0
USB_RXMAXP9_MAXLOAD
Maximum Payload
0
11
USB0RXTYPE1
USB Host Configure Receive Type Endpoint 1
0x11C
8
read-write
n
0x0
0x0
USB_RXTYPE1_PROTO
Protocol
4
6
USB_RXTYPE1_PROTO_CTRL
Control
0x0
USB_RXTYPE1_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE1_PROTO_BULK
Bulk
0x2
USB_RXTYPE1_PROTO_INT
Interrupt
0x3
USB_RXTYPE1_SPEED
Operating Speed
6
8
USB_RXTYPE1_SPEED_DFLT
Default
0x0
USB_RXTYPE1_SPEED_FULL
Full
0x2
USB_RXTYPE1_SPEED_LOW
Low
0x3
USB_RXTYPE1_TEP
Target Endpoint Number
0
4
USB0RXTYPE10
USB Host Configure Receive Type Endpoint 10
0x1AC
8
read-write
n
0x0
0x0
USB_RXTYPE10_PROTO
Protocol
4
6
USB_RXTYPE10_PROTO_CTRL
Control
0x0
USB_RXTYPE10_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE10_PROTO_BULK
Bulk
0x2
USB_RXTYPE10_PROTO_INT
Interrupt
0x3
USB_RXTYPE10_SPEED
Operating Speed
6
8
USB_RXTYPE10_SPEED_DFLT
Default
0x0
USB_RXTYPE10_SPEED_FULL
Full
0x2
USB_RXTYPE10_SPEED_LOW
Low
0x3
USB_RXTYPE10_TEP
Target Endpoint Number
0
4
USB0RXTYPE11
USB Host Configure Receive Type Endpoint 11
0x1BC
8
read-write
n
0x0
0x0
USB_RXTYPE11_PROTO
Protocol
4
6
USB_RXTYPE11_PROTO_CTRL
Control
0x0
USB_RXTYPE11_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE11_PROTO_BULK
Bulk
0x2
USB_RXTYPE11_PROTO_INT
Interrupt
0x3
USB_RXTYPE11_SPEED
Operating Speed
6
8
USB_RXTYPE11_SPEED_DFLT
Default
0x0
USB_RXTYPE11_SPEED_FULL
Full
0x2
USB_RXTYPE11_SPEED_LOW
Low
0x3
USB_RXTYPE11_TEP
Target Endpoint Number
0
4
USB0RXTYPE12
USB Host Configure Receive Type Endpoint 12
0x1CC
8
read-write
n
0x0
0x0
USB_RXTYPE12_PROTO
Protocol
4
6
USB_RXTYPE12_PROTO_CTRL
Control
0x0
USB_RXTYPE12_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE12_PROTO_BULK
Bulk
0x2
USB_RXTYPE12_PROTO_INT
Interrupt
0x3
USB_RXTYPE12_SPEED
Operating Speed
6
8
USB_RXTYPE12_SPEED_DFLT
Default
0x0
USB_RXTYPE12_SPEED_FULL
Full
0x2
USB_RXTYPE12_SPEED_LOW
Low
0x3
USB_RXTYPE12_TEP
Target Endpoint Number
0
4
USB0RXTYPE13
USB Host Configure Receive Type Endpoint 13
0x1DC
8
read-write
n
0x0
0x0
USB_RXTYPE13_PROTO
Protocol
4
6
USB_RXTYPE13_PROTO_CTRL
Control
0x0
USB_RXTYPE13_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE13_PROTO_BULK
Bulk
0x2
USB_RXTYPE13_PROTO_INT
Interrupt
0x3
USB_RXTYPE13_SPEED
Operating Speed
6
8
USB_RXTYPE13_SPEED_DFLT
Default
0x0
USB_RXTYPE13_SPEED_FULL
Full
0x2
USB_RXTYPE13_SPEED_LOW
Low
0x3
USB_RXTYPE13_TEP
Target Endpoint Number
0
4
USB0RXTYPE14
USB Host Configure Receive Type Endpoint 14
0x1EC
8
read-write
n
0x0
0x0
USB_RXTYPE14_PROTO
Protocol
4
6
USB_RXTYPE14_PROTO_CTRL
Control
0x0
USB_RXTYPE14_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE14_PROTO_BULK
Bulk
0x2
USB_RXTYPE14_PROTO_INT
Interrupt
0x3
USB_RXTYPE14_SPEED
Operating Speed
6
8
USB_RXTYPE14_SPEED_DFLT
Default
0x0
USB_RXTYPE14_SPEED_FULL
Full
0x2
USB_RXTYPE14_SPEED_LOW
Low
0x3
USB_RXTYPE14_TEP
Target Endpoint Number
0
4
USB0RXTYPE15
USB Host Configure Receive Type Endpoint 15
0x1FC
8
read-write
n
0x0
0x0
USB_RXTYPE15_PROTO
Protocol
4
6
USB_RXTYPE15_PROTO_CTRL
Control
0x0
USB_RXTYPE15_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE15_PROTO_BULK
Bulk
0x2
USB_RXTYPE15_PROTO_INT
Interrupt
0x3
USB_RXTYPE15_SPEED
Operating Speed
6
8
USB_RXTYPE15_SPEED_DFLT
Default
0x0
USB_RXTYPE15_SPEED_FULL
Full
0x2
USB_RXTYPE15_SPEED_LOW
Low
0x3
USB_RXTYPE15_TEP
Target Endpoint Number
0
4
USB0RXTYPE2
USB Host Configure Receive Type Endpoint 2
0x12C
8
read-write
n
0x0
0x0
USB_RXTYPE2_PROTO
Protocol
4
6
USB_RXTYPE2_PROTO_CTRL
Control
0x0
USB_RXTYPE2_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE2_PROTO_BULK
Bulk
0x2
USB_RXTYPE2_PROTO_INT
Interrupt
0x3
USB_RXTYPE2_SPEED
Operating Speed
6
8
USB_RXTYPE2_SPEED_DFLT
Default
0x0
USB_RXTYPE2_SPEED_FULL
Full
0x2
USB_RXTYPE2_SPEED_LOW
Low
0x3
USB_RXTYPE2_TEP
Target Endpoint Number
0
4
USB0RXTYPE3
USB Host Configure Receive Type Endpoint 3
0x13C
8
read-write
n
0x0
0x0
USB_RXTYPE3_PROTO
Protocol
4
6
USB_RXTYPE3_PROTO_CTRL
Control
0x0
USB_RXTYPE3_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE3_PROTO_BULK
Bulk
0x2
USB_RXTYPE3_PROTO_INT
Interrupt
0x3
USB_RXTYPE3_SPEED
Operating Speed
6
8
USB_RXTYPE3_SPEED_DFLT
Default
0x0
USB_RXTYPE3_SPEED_FULL
Full
0x2
USB_RXTYPE3_SPEED_LOW
Low
0x3
USB_RXTYPE3_TEP
Target Endpoint Number
0
4
USB0RXTYPE4
USB Host Configure Receive Type Endpoint 4
0x14C
8
read-write
n
0x0
0x0
USB_RXTYPE4_PROTO
Protocol
4
6
USB_RXTYPE4_PROTO_CTRL
Control
0x0
USB_RXTYPE4_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE4_PROTO_BULK
Bulk
0x2
USB_RXTYPE4_PROTO_INT
Interrupt
0x3
USB_RXTYPE4_SPEED
Operating Speed
6
8
USB_RXTYPE4_SPEED_DFLT
Default
0x0
USB_RXTYPE4_SPEED_FULL
Full
0x2
USB_RXTYPE4_SPEED_LOW
Low
0x3
USB_RXTYPE4_TEP
Target Endpoint Number
0
4
USB0RXTYPE5
USB Host Configure Receive Type Endpoint 5
0x15C
8
read-write
n
0x0
0x0
USB_RXTYPE5_PROTO
Protocol
4
6
USB_RXTYPE5_PROTO_CTRL
Control
0x0
USB_RXTYPE5_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE5_PROTO_BULK
Bulk
0x2
USB_RXTYPE5_PROTO_INT
Interrupt
0x3
USB_RXTYPE5_SPEED
Operating Speed
6
8
USB_RXTYPE5_SPEED_DFLT
Default
0x0
USB_RXTYPE5_SPEED_FULL
Full
0x2
USB_RXTYPE5_SPEED_LOW
Low
0x3
USB_RXTYPE5_TEP
Target Endpoint Number
0
4
USB0RXTYPE6
USB Host Configure Receive Type Endpoint 6
0x16C
8
read-write
n
0x0
0x0
USB_RXTYPE6_PROTO
Protocol
4
6
USB_RXTYPE6_PROTO_CTRL
Control
0x0
USB_RXTYPE6_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE6_PROTO_BULK
Bulk
0x2
USB_RXTYPE6_PROTO_INT
Interrupt
0x3
USB_RXTYPE6_SPEED
Operating Speed
6
8
USB_RXTYPE6_SPEED_DFLT
Default
0x0
USB_RXTYPE6_SPEED_FULL
Full
0x2
USB_RXTYPE6_SPEED_LOW
Low
0x3
USB_RXTYPE6_TEP
Target Endpoint Number
0
4
USB0RXTYPE7
USB Host Configure Receive Type Endpoint 7
0x17C
8
read-write
n
0x0
0x0
USB_RXTYPE7_PROTO
Protocol
4
6
USB_RXTYPE7_PROTO_CTRL
Control
0x0
USB_RXTYPE7_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE7_PROTO_BULK
Bulk
0x2
USB_RXTYPE7_PROTO_INT
Interrupt
0x3
USB_RXTYPE7_SPEED
Operating Speed
6
8
USB_RXTYPE7_SPEED_DFLT
Default
0x0
USB_RXTYPE7_SPEED_FULL
Full
0x2
USB_RXTYPE7_SPEED_LOW
Low
0x3
USB_RXTYPE7_TEP
Target Endpoint Number
0
4
USB0RXTYPE8
USB Host Configure Receive Type Endpoint 8
0x18C
8
read-write
n
0x0
0x0
USB_RXTYPE8_PROTO
Protocol
4
6
USB_RXTYPE8_PROTO_CTRL
Control
0x0
USB_RXTYPE8_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE8_PROTO_BULK
Bulk
0x2
USB_RXTYPE8_PROTO_INT
Interrupt
0x3
USB_RXTYPE8_SPEED
Operating Speed
6
8
USB_RXTYPE8_SPEED_DFLT
Default
0x0
USB_RXTYPE8_SPEED_FULL
Full
0x2
USB_RXTYPE8_SPEED_LOW
Low
0x3
USB_RXTYPE8_TEP
Target Endpoint Number
0
4
USB0RXTYPE9
USB Host Configure Receive Type Endpoint 9
0x19C
8
read-write
n
0x0
0x0
USB_RXTYPE9_PROTO
Protocol
4
6
USB_RXTYPE9_PROTO_CTRL
Control
0x0
USB_RXTYPE9_PROTO_ISOC
Isochronous
0x1
USB_RXTYPE9_PROTO_BULK
Bulk
0x2
USB_RXTYPE9_PROTO_INT
Interrupt
0x3
USB_RXTYPE9_SPEED
Operating Speed
6
8
USB_RXTYPE9_SPEED_DFLT
Default
0x0
USB_RXTYPE9_SPEED_FULL
Full
0x2
USB_RXTYPE9_SPEED_LOW
Low
0x3
USB_RXTYPE9_TEP
Target Endpoint Number
0
4
USB0TEST
USB Test Mode
0xF
8
read-write
n
0x0
0x0
USB_TEST_FIFOACC
FIFO Access
6
7
USB_TEST_FORCEFS
Force Full-Speed Mode
5
6
USB_TEST_FORCEH
Force Host Mode
7
8
USB0TXCSRH1
USB Transmit Control and Status Endpoint 1 High
0x113
8
read-write
n
0x0
0x0
USB_TXCSRH1_AUTOSET
Auto Set
7
8
USB_TXCSRH1_DMAEN
DMA Request Enable
4
5
USB_TXCSRH1_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH1_DT
Data Toggle
0
1
USB_TXCSRH1_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH1_FDT
Force Data Toggle
3
4
USB_TXCSRH1_ISO
Isochronous Transfers
6
7
USB_TXCSRH1_MODE
Mode
5
6
USB0TXCSRH10
USB Transmit Control and Status Endpoint 10 High
0x1A3
8
read-write
n
0x0
0x0
USB_TXCSRH10_AUTOSET
Auto Set
7
8
USB_TXCSRH10_DMAEN
DMA Request Enable
4
5
USB_TXCSRH10_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH10_DT
Data Toggle
0
1
USB_TXCSRH10_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH10_FDT
Force Data Toggle
3
4
USB_TXCSRH10_ISO
Isochronous Transfers
6
7
USB_TXCSRH10_MODE
Mode
5
6
USB0TXCSRH11
USB Transmit Control and Status Endpoint 11 High
0x1B3
8
read-write
n
0x0
0x0
USB_TXCSRH11_AUTOSET
Auto Set
7
8
USB_TXCSRH11_DMAEN
DMA Request Enable
4
5
USB_TXCSRH11_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH11_DT
Data Toggle
0
1
USB_TXCSRH11_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH11_FDT
Force Data Toggle
3
4
USB_TXCSRH11_ISO
Isochronous Transfers
6
7
USB_TXCSRH11_MODE
Mode
5
6
USB0TXCSRH12
USB Transmit Control and Status Endpoint 12 High
0x1C3
8
read-write
n
0x0
0x0
USB_TXCSRH12_AUTOSET
Auto Set
7
8
USB_TXCSRH12_DMAEN
DMA Request Enable
4
5
USB_TXCSRH12_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH12_DT
Data Toggle
0
1
USB_TXCSRH12_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH12_FDT
Force Data Toggle
3
4
USB_TXCSRH12_ISO
Isochronous Transfers
6
7
USB_TXCSRH12_MODE
Mode
5
6
USB0TXCSRH13
USB Transmit Control and Status Endpoint 13 High
0x1D3
8
read-write
n
0x0
0x0
USB_TXCSRH13_AUTOSET
Auto Set
7
8
USB_TXCSRH13_DMAEN
DMA Request Enable
4
5
USB_TXCSRH13_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH13_DT
Data Toggle
0
1
USB_TXCSRH13_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH13_FDT
Force Data Toggle
3
4
USB_TXCSRH13_ISO
Isochronous Transfers
6
7
USB_TXCSRH13_MODE
Mode
5
6
USB0TXCSRH14
USB Transmit Control and Status Endpoint 14 High
0x1E3
8
read-write
n
0x0
0x0
USB_TXCSRH14_AUTOSET
Auto Set
7
8
USB_TXCSRH14_DMAEN
DMA Request Enable
4
5
USB_TXCSRH14_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH14_DT
Data Toggle
0
1
USB_TXCSRH14_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH14_FDT
Force Data Toggle
3
4
USB_TXCSRH14_ISO
Isochronous Transfers
6
7
USB_TXCSRH14_MODE
Mode
5
6
USB0TXCSRH15
USB Transmit Control and Status Endpoint 15 High
0x1F3
8
read-write
n
0x0
0x0
USB_TXCSRH15_AUTOSET
Auto Set
7
8
USB_TXCSRH15_DMAEN
DMA Request Enable
4
5
USB_TXCSRH15_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH15_DT
Data Toggle
0
1
USB_TXCSRH15_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH15_FDT
Force Data Toggle
3
4
USB_TXCSRH15_ISO
Isochronous Transfers
6
7
USB_TXCSRH15_MODE
Mode
5
6
USB0TXCSRH2
USB Transmit Control and Status Endpoint 2 High
0x123
8
read-write
n
0x0
0x0
USB_TXCSRH2_AUTOSET
Auto Set
7
8
USB_TXCSRH2_DMAEN
DMA Request Enable
4
5
USB_TXCSRH2_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH2_DT
Data Toggle
0
1
USB_TXCSRH2_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH2_FDT
Force Data Toggle
3
4
USB_TXCSRH2_ISO
Isochronous Transfers
6
7
USB_TXCSRH2_MODE
Mode
5
6
USB0TXCSRH3
USB Transmit Control and Status Endpoint 3 High
0x133
8
read-write
n
0x0
0x0
USB_TXCSRH3_AUTOSET
Auto Set
7
8
USB_TXCSRH3_DMAEN
DMA Request Enable
4
5
USB_TXCSRH3_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH3_DT
Data Toggle
0
1
USB_TXCSRH3_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH3_FDT
Force Data Toggle
3
4
USB_TXCSRH3_ISO
Isochronous Transfers
6
7
USB_TXCSRH3_MODE
Mode
5
6
USB0TXCSRH4
USB Transmit Control and Status Endpoint 4 High
0x143
8
read-write
n
0x0
0x0
USB_TXCSRH4_AUTOSET
Auto Set
7
8
USB_TXCSRH4_DMAEN
DMA Request Enable
4
5
USB_TXCSRH4_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH4_DT
Data Toggle
0
1
USB_TXCSRH4_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH4_FDT
Force Data Toggle
3
4
USB_TXCSRH4_ISO
Isochronous Transfers
6
7
USB_TXCSRH4_MODE
Mode
5
6
USB0TXCSRH5
USB Transmit Control and Status Endpoint 5 High
0x153
8
read-write
n
0x0
0x0
USB_TXCSRH5_AUTOSET
Auto Set
7
8
USB_TXCSRH5_DMAEN
DMA Request Enable
4
5
USB_TXCSRH5_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH5_DT
Data Toggle
0
1
USB_TXCSRH5_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH5_FDT
Force Data Toggle
3
4
USB_TXCSRH5_ISO
Isochronous Transfers
6
7
USB_TXCSRH5_MODE
Mode
5
6
USB0TXCSRH6
USB Transmit Control and Status Endpoint 6 High
0x163
8
read-write
n
0x0
0x0
USB_TXCSRH6_AUTOSET
Auto Set
7
8
USB_TXCSRH6_DMAEN
DMA Request Enable
4
5
USB_TXCSRH6_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH6_DT
Data Toggle
0
1
USB_TXCSRH6_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH6_FDT
Force Data Toggle
3
4
USB_TXCSRH6_ISO
Isochronous Transfers
6
7
USB_TXCSRH6_MODE
Mode
5
6
USB0TXCSRH7
USB Transmit Control and Status Endpoint 7 High
0x173
8
read-write
n
0x0
0x0
USB_TXCSRH7_AUTOSET
Auto Set
7
8
USB_TXCSRH7_DMAEN
DMA Request Enable
4
5
USB_TXCSRH7_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH7_DT
Data Toggle
0
1
USB_TXCSRH7_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH7_FDT
Force Data Toggle
3
4
USB_TXCSRH7_ISO
Isochronous Transfers
6
7
USB_TXCSRH7_MODE
Mode
5
6
USB0TXCSRH8
USB Transmit Control and Status Endpoint 8 High
0x183
8
read-write
n
0x0
0x0
USB_TXCSRH8_AUTOSET
Auto Set
7
8
USB_TXCSRH8_DMAEN
DMA Request Enable
4
5
USB_TXCSRH8_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH8_DT
Data Toggle
0
1
USB_TXCSRH8_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH8_FDT
Force Data Toggle
3
4
USB_TXCSRH8_ISO
Isochronous Transfers
6
7
USB_TXCSRH8_MODE
Mode
5
6
USB0TXCSRH9
USB Transmit Control and Status Endpoint 9 High
0x193
8
read-write
n
0x0
0x0
USB_TXCSRH9_AUTOSET
Auto Set
7
8
USB_TXCSRH9_DMAEN
DMA Request Enable
4
5
USB_TXCSRH9_DMAMOD
DMA Request Mode
2
3
USB_TXCSRH9_DT
Data Toggle
0
1
USB_TXCSRH9_DTWE
Data Toggle Write Enable
1
2
USB_TXCSRH9_FDT
Force Data Toggle
3
4
USB_TXCSRH9_ISO
Isochronous Transfers
6
7
USB_TXCSRH9_MODE
Mode
5
6
USB0TXCSRL1
USB Transmit Control and Status Endpoint 1 Low
0x112
8
read-write
n
0x0
0x0
USB_TXCSRL1_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL1_ERROR
Error
2
3
USB_TXCSRL1_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL1_FLUSH
Flush FIFO
3
4
USB_TXCSRL1_NAKTO
NAK Timeout
7
8
USB_TXCSRL1_SETUP
Setup Packet
4
5
USB_TXCSRL1_STALLED
Endpoint Stalled
5
6
USB_TXCSRL1_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL10
USB Transmit Control and Status Endpoint 10 Low
0x1A2
8
read-write
n
0x0
0x0
USB_TXCSRL10_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL10_ERROR
Error
2
3
USB_TXCSRL10_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL10_FLUSH
Flush FIFO
3
4
USB_TXCSRL10_NAKTO
NAK Timeout
7
8
USB_TXCSRL10_SETUP
Setup Packet
4
5
USB_TXCSRL10_STALLED
Endpoint Stalled
5
6
USB_TXCSRL10_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL11
USB Transmit Control and Status Endpoint 11 Low
0x1B2
8
read-write
n
0x0
0x0
USB_TXCSRL11_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL11_ERROR
Error
2
3
USB_TXCSRL11_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL11_FLUSH
Flush FIFO
3
4
USB_TXCSRL11_NAKTO
NAK Timeout
7
8
USB_TXCSRL11_SETUP
Setup Packet
4
5
USB_TXCSRL11_STALLED
Endpoint Stalled
5
6
USB_TXCSRL11_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL12
USB Transmit Control and Status Endpoint 12 Low
0x1C2
8
read-write
n
0x0
0x0
USB_TXCSRL12_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL12_ERROR
Error
2
3
USB_TXCSRL12_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL12_FLUSH
Flush FIFO
3
4
USB_TXCSRL12_NAKTO
NAK Timeout
7
8
USB_TXCSRL12_SETUP
Setup Packet
4
5
USB_TXCSRL12_STALLED
Endpoint Stalled
5
6
USB_TXCSRL12_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL13
USB Transmit Control and Status Endpoint 13 Low
0x1D2
8
read-write
n
0x0
0x0
USB_TXCSRL13_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL13_ERROR
Error
2
3
USB_TXCSRL13_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL13_FLUSH
Flush FIFO
3
4
USB_TXCSRL13_NAKTO
NAK Timeout
7
8
USB_TXCSRL13_SETUP
Setup Packet
4
5
USB_TXCSRL13_STALLED
Endpoint Stalled
5
6
USB_TXCSRL13_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL14
USB Transmit Control and Status Endpoint 14 Low
0x1E2
8
read-write
n
0x0
0x0
USB_TXCSRL14_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL14_ERROR
Error
2
3
USB_TXCSRL14_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL14_FLUSH
Flush FIFO
3
4
USB_TXCSRL14_NAKTO
NAK Timeout
7
8
USB_TXCSRL14_SETUP
Setup Packet
4
5
USB_TXCSRL14_STALLED
Endpoint Stalled
5
6
USB_TXCSRL14_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL15
USB Transmit Control and Status Endpoint 15 Low
0x1F2
8
read-write
n
0x0
0x0
USB_TXCSRL15_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL15_ERROR
Error
2
3
USB_TXCSRL15_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL15_FLUSH
Flush FIFO
3
4
USB_TXCSRL15_NAKTO
NAK Timeout
7
8
USB_TXCSRL15_SETUP
Setup Packet
4
5
USB_TXCSRL15_STALLED
Endpoint Stalled
5
6
USB_TXCSRL15_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL2
USB Transmit Control and Status Endpoint 2 Low
0x122
8
read-write
n
0x0
0x0
USB_TXCSRL2_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL2_ERROR
Error
2
3
USB_TXCSRL2_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL2_FLUSH
Flush FIFO
3
4
USB_TXCSRL2_NAKTO
NAK Timeout
7
8
USB_TXCSRL2_SETUP
Setup Packet
4
5
USB_TXCSRL2_STALLED
Endpoint Stalled
5
6
USB_TXCSRL2_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL3
USB Transmit Control and Status Endpoint 3 Low
0x132
8
read-write
n
0x0
0x0
USB_TXCSRL3_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL3_ERROR
Error
2
3
USB_TXCSRL3_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL3_FLUSH
Flush FIFO
3
4
USB_TXCSRL3_NAKTO
NAK Timeout
7
8
USB_TXCSRL3_SETUP
Setup Packet
4
5
USB_TXCSRL3_STALLED
Endpoint Stalled
5
6
USB_TXCSRL3_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL4
USB Transmit Control and Status Endpoint 4 Low
0x142
8
read-write
n
0x0
0x0
USB_TXCSRL4_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL4_ERROR
Error
2
3
USB_TXCSRL4_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL4_FLUSH
Flush FIFO
3
4
USB_TXCSRL4_NAKTO
NAK Timeout
7
8
USB_TXCSRL4_SETUP
Setup Packet
4
5
USB_TXCSRL4_STALLED
Endpoint Stalled
5
6
USB_TXCSRL4_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL5
USB Transmit Control and Status Endpoint 5 Low
0x152
8
read-write
n
0x0
0x0
USB_TXCSRL5_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL5_ERROR
Error
2
3
USB_TXCSRL5_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL5_FLUSH
Flush FIFO
3
4
USB_TXCSRL5_NAKTO
NAK Timeout
7
8
USB_TXCSRL5_SETUP
Setup Packet
4
5
USB_TXCSRL5_STALLED
Endpoint Stalled
5
6
USB_TXCSRL5_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL6
USB Transmit Control and Status Endpoint 6 Low
0x162
8
read-write
n
0x0
0x0
USB_TXCSRL6_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL6_ERROR
Error
2
3
USB_TXCSRL6_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL6_FLUSH
Flush FIFO
3
4
USB_TXCSRL6_NAKTO
NAK Timeout
7
8
USB_TXCSRL6_SETUP
Setup Packet
4
5
USB_TXCSRL6_STALLED
Endpoint Stalled
5
6
USB_TXCSRL6_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL7
USB Transmit Control and Status Endpoint 7 Low
0x172
8
read-write
n
0x0
0x0
USB_TXCSRL7_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL7_ERROR
Error
2
3
USB_TXCSRL7_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL7_FLUSH
Flush FIFO
3
4
USB_TXCSRL7_NAKTO
NAK Timeout
7
8
USB_TXCSRL7_SETUP
Setup Packet
4
5
USB_TXCSRL7_STALLED
Endpoint Stalled
5
6
USB_TXCSRL7_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL8
USB Transmit Control and Status Endpoint 8 Low
0x182
8
read-write
n
0x0
0x0
USB_TXCSRL8_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL8_ERROR
Error
2
3
USB_TXCSRL8_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL8_FLUSH
Flush FIFO
3
4
USB_TXCSRL8_NAKTO
NAK Timeout
7
8
USB_TXCSRL8_SETUP
Setup Packet
4
5
USB_TXCSRL8_STALLED
Endpoint Stalled
5
6
USB_TXCSRL8_TXRDY
Transmit Packet Ready
0
1
USB0TXCSRL9
USB Transmit Control and Status Endpoint 9 Low
0x192
8
read-write
n
0x0
0x0
USB_TXCSRL9_CLRDT
Clear Data Toggle
6
7
USB_TXCSRL9_ERROR
Error
2
3
USB_TXCSRL9_FIFONE
FIFO Not Empty
1
2
USB_TXCSRL9_FLUSH
Flush FIFO
3
4
USB_TXCSRL9_NAKTO
NAK Timeout
7
8
USB_TXCSRL9_SETUP
Setup Packet
4
5
USB_TXCSRL9_STALLED
Endpoint Stalled
5
6
USB_TXCSRL9_TXRDY
Transmit Packet Ready
0
1
USB0TXDPKTBUFDIS
USB Transmit Double Packet Buffer Disable
0x342
16
read-write
n
0x0
0x0
USB_TXDPKTBUFDIS_EP1
EP1 TX Double-Packet Buffer Disable
1
2
USB_TXDPKTBUFDIS_EP10
EP10 TX Double-Packet Buffer Disable
10
11
USB_TXDPKTBUFDIS_EP11
EP11 TX Double-Packet Buffer Disable
11
12
USB_TXDPKTBUFDIS_EP12
EP12 TX Double-Packet Buffer Disable
12
13
USB_TXDPKTBUFDIS_EP13
EP13 TX Double-Packet Buffer Disable
13
14
USB_TXDPKTBUFDIS_EP14
EP14 TX Double-Packet Buffer Disable
14
15
USB_TXDPKTBUFDIS_EP15
EP15 TX Double-Packet Buffer Disable
15
16
USB_TXDPKTBUFDIS_EP2
EP2 TX Double-Packet Buffer Disable
2
3
USB_TXDPKTBUFDIS_EP3
EP3 TX Double-Packet Buffer Disable
3
4
USB_TXDPKTBUFDIS_EP4
EP4 TX Double-Packet Buffer Disable
4
5
USB_TXDPKTBUFDIS_EP5
EP5 TX Double-Packet Buffer Disable
5
6
USB_TXDPKTBUFDIS_EP6
EP6 TX Double-Packet Buffer Disable
6
7
USB_TXDPKTBUFDIS_EP7
EP7 TX Double-Packet Buffer Disable
7
8
USB_TXDPKTBUFDIS_EP8
EP8 TX Double-Packet Buffer Disable
8
9
USB_TXDPKTBUFDIS_EP9
EP9 TX Double-Packet Buffer Disable
9
10
USB0TXFIFOADD
USB Transmit FIFO Start Address
0x64
16
read-write
n
0x0
0x0
USB_TXFIFOADD_ADDR
Transmit/Receive Start Address
0
9
USB0TXFIFOSZ
USB Transmit Dynamic FIFO Sizing
0x62
8
read-write
n
0x0
0x0
USB_TXFIFOSZ_DPB
Double Packet Buffer Support
4
5
USB_TXFIFOSZ_SIZE
Max Packet Size
0
4
USB_TXFIFOSZ_SIZE_8
8
0x0
USB_TXFIFOSZ_SIZE_16
16
0x1
USB_TXFIFOSZ_SIZE_32
32
0x2
USB_TXFIFOSZ_SIZE_64
64
0x3
USB_TXFIFOSZ_SIZE_128
128
0x4
USB_TXFIFOSZ_SIZE_256
256
0x5
USB_TXFIFOSZ_SIZE_512
512
0x6
USB_TXFIFOSZ_SIZE_1024
1024
0x7
USB_TXFIFOSZ_SIZE_2048
2048
0x8
USB0TXFUNCADDR0
USB Transmit Functional Address Endpoint 0
0x80
8
read-write
n
0x0
0x0
USB_TXFUNCADDR0_ADDR
Device Address
0
7
USB0TXFUNCADDR1
USB Transmit Functional Address Endpoint 1
0x88
8
read-write
n
0x0
0x0
USB_TXFUNCADDR1_ADDR
Device Address
0
7
USB0TXFUNCADDR10
USB Transmit Functional Address Endpoint 10
0xD0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR10_ADDR
Device Address
0
7
USB0TXFUNCADDR11
USB Transmit Functional Address Endpoint 11
0xD8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR11_ADDR
Device Address
0
7
USB0TXFUNCADDR12
USB Transmit Functional Address Endpoint 12
0xE0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR12_ADDR
Device Address
0
7
USB0TXFUNCADDR13
USB Transmit Functional Address Endpoint 13
0xE8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR13_ADDR
Device Address
0
7
USB0TXFUNCADDR14
USB Transmit Functional Address Endpoint 14
0xF0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR14_ADDR
Device Address
0
7
USB0TXFUNCADDR15
USB Transmit Functional Address Endpoint 15
0xF8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR15_ADDR
Device Address
0
7
USB0TXFUNCADDR2
USB Transmit Functional Address Endpoint 2
0x90
8
read-write
n
0x0
0x0
USB_TXFUNCADDR2_ADDR
Device Address
0
7
USB0TXFUNCADDR3
USB Transmit Functional Address Endpoint 3
0x98
8
read-write
n
0x0
0x0
USB_TXFUNCADDR3_ADDR
Device Address
0
7
USB0TXFUNCADDR4
USB Transmit Functional Address Endpoint 4
0xA0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR4_ADDR
Device Address
0
7
USB0TXFUNCADDR5
USB Transmit Functional Address Endpoint 5
0xA8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR5_ADDR
Device Address
0
7
USB0TXFUNCADDR6
USB Transmit Functional Address Endpoint 6
0xB0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR6_ADDR
Device Address
0
7
USB0TXFUNCADDR7
USB Transmit Functional Address Endpoint 7
0xB8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR7_ADDR
Device Address
0
7
USB0TXFUNCADDR8
USB Transmit Functional Address Endpoint 8
0xC0
8
read-write
n
0x0
0x0
USB_TXFUNCADDR8_ADDR
Device Address
0
7
USB0TXFUNCADDR9
USB Transmit Functional Address Endpoint 9
0xC8
8
read-write
n
0x0
0x0
USB_TXFUNCADDR9_ADDR
Device Address
0
7
USB0TXHUBADDR0
USB Transmit Hub Address Endpoint 0
0x82
8
read-write
n
0x0
0x0
USB_TXHUBADDR0_ADDR
Hub Address
0
7
USB_TXHUBADDR0_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR1
USB Transmit Hub Address Endpoint 1
0x8A
8
read-write
n
0x0
0x0
USB_TXHUBADDR1_ADDR
Hub Address
0
7
USB_TXHUBADDR1_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR10
USB Transmit Hub Address Endpoint 10
0xD2
8
read-write
n
0x0
0x0
USB_TXHUBADDR10_ADDR
Hub Address
0
7
USB_TXHUBADDR10_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR11
USB Transmit Hub Address Endpoint 11
0xDA
8
read-write
n
0x0
0x0
USB_TXHUBADDR11_ADDR
Hub Address
0
7
USB_TXHUBADDR11_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR12
USB Transmit Hub Address Endpoint 12
0xE2
8
read-write
n
0x0
0x0
USB_TXHUBADDR12_ADDR
Hub Address
0
7
USB_TXHUBADDR12_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR13
USB Transmit Hub Address Endpoint 13
0xEA
8
read-write
n
0x0
0x0
USB_TXHUBADDR13_ADDR
Hub Address
0
7
USB_TXHUBADDR13_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR14
USB Transmit Hub Address Endpoint 14
0xF2
8
read-write
n
0x0
0x0
USB_TXHUBADDR14_ADDR
Hub Address
0
7
USB_TXHUBADDR14_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR15
USB Transmit Hub Address Endpoint 15
0xFA
8
read-write
n
0x0
0x0
USB_TXHUBADDR15_ADDR
Hub Address
0
7
USB_TXHUBADDR15_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR2
USB Transmit Hub Address Endpoint 2
0x92
8
read-write
n
0x0
0x0
USB_TXHUBADDR2_ADDR
Hub Address
0
7
USB_TXHUBADDR2_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR3
USB Transmit Hub Address Endpoint 3
0x9A
8
read-write
n
0x0
0x0
USB_TXHUBADDR3_ADDR
Hub Address
0
7
USB_TXHUBADDR3_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR4
USB Transmit Hub Address Endpoint 4
0xA2
8
read-write
n
0x0
0x0
USB_TXHUBADDR4_ADDR
Hub Address
0
7
USB_TXHUBADDR4_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR5
USB Transmit Hub Address Endpoint 5
0xAA
8
read-write
n
0x0
0x0
USB_TXHUBADDR5_ADDR
Hub Address
0
7
USB_TXHUBADDR5_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR6
USB Transmit Hub Address Endpoint 6
0xB2
8
read-write
n
0x0
0x0
USB_TXHUBADDR6_ADDR
Hub Address
0
7
USB_TXHUBADDR6_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR7
USB Transmit Hub Address Endpoint 7
0xBA
8
read-write
n
0x0
0x0
USB_TXHUBADDR7_ADDR
Hub Address
0
7
USB_TXHUBADDR7_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR8
USB Transmit Hub Address Endpoint 8
0xC2
8
read-write
n
0x0
0x0
USB_TXHUBADDR8_ADDR
Hub Address
0
7
USB_TXHUBADDR8_MULTTRAN
Multiple Translators
7
8
USB0TXHUBADDR9
USB Transmit Hub Address Endpoint 9
0xCA
8
read-write
n
0x0
0x0
USB_TXHUBADDR9_ADDR
Hub Address
0
7
USB_TXHUBADDR9_MULTTRAN
Multiple Translators
7
8
USB0TXHUBPORT0
USB Transmit Hub Port Endpoint 0
0x83
8
read-write
n
0x0
0x0
USB_TXHUBPORT0_PORT
Hub Port
0
7
USB0TXHUBPORT1
USB Transmit Hub Port Endpoint 1
0x8B
8
read-write
n
0x0
0x0
USB_TXHUBPORT1_PORT
Hub Port
0
7
USB0TXHUBPORT10
USB Transmit Hub Port Endpoint 10
0xD3
8
read-write
n
0x0
0x0
USB_TXHUBPORT10_PORT
Hub Port
0
7
USB0TXHUBPORT11
USB Transmit Hub Port Endpoint 11
0xDB
8
read-write
n
0x0
0x0
USB_TXHUBPORT11_PORT
Hub Port
0
7
USB0TXHUBPORT12
USB Transmit Hub Port Endpoint 12
0xE3
8
read-write
n
0x0
0x0
USB_TXHUBPORT12_PORT
Hub Port
0
7
USB0TXHUBPORT13
USB Transmit Hub Port Endpoint 13
0xEB
8
read-write
n
0x0
0x0
USB_TXHUBPORT13_PORT
Hub Port
0
7
USB0TXHUBPORT14
USB Transmit Hub Port Endpoint 14
0xF3
8
read-write
n
0x0
0x0
USB_TXHUBPORT14_PORT
Hub Port
0
7
USB0TXHUBPORT15
USB Transmit Hub Port Endpoint 15
0xFB
8
read-write
n
0x0
0x0
USB_TXHUBPORT15_PORT
Hub Port
0
7
USB0TXHUBPORT2
USB Transmit Hub Port Endpoint 2
0x93
8
read-write
n
0x0
0x0
USB_TXHUBPORT2_PORT
Hub Port
0
7
USB0TXHUBPORT3
USB Transmit Hub Port Endpoint 3
0x9B
8
read-write
n
0x0
0x0
USB_TXHUBPORT3_PORT
Hub Port
0
7
USB0TXHUBPORT4
USB Transmit Hub Port Endpoint 4
0xA3
8
read-write
n
0x0
0x0
USB_TXHUBPORT4_PORT
Hub Port
0
7
USB0TXHUBPORT5
USB Transmit Hub Port Endpoint 5
0xAB
8
read-write
n
0x0
0x0
USB_TXHUBPORT5_PORT
Hub Port
0
7
USB0TXHUBPORT6
USB Transmit Hub Port Endpoint 6
0xB3
8
read-write
n
0x0
0x0
USB_TXHUBPORT6_PORT
Hub Port
0
7
USB0TXHUBPORT7
USB Transmit Hub Port Endpoint 7
0xBB
8
read-write
n
0x0
0x0
USB_TXHUBPORT7_PORT
Hub Port
0
7
USB0TXHUBPORT8
USB Transmit Hub Port Endpoint 8
0xC3
8
read-write
n
0x0
0x0
USB_TXHUBPORT8_PORT
Hub Port
0
7
USB0TXHUBPORT9
USB Transmit Hub Port Endpoint 9
0xCB
8
read-write
n
0x0
0x0
USB_TXHUBPORT9_PORT
Hub Port
0
7
USB0TXIE
USB Transmit Interrupt Enable
0x6
16
read-write
n
0x0
0x0
USB_TXIE_EP0
TX and RX Endpoint 0 Interrupt Enable
0
1
USB_TXIE_EP1
TX Endpoint 1 Interrupt Enable
1
2
USB_TXIE_EP10
TX Endpoint 10 Interrupt Enable
10
11
USB_TXIE_EP11
TX Endpoint 11 Interrupt Enable
11
12
USB_TXIE_EP12
TX Endpoint 12 Interrupt Enable
12
13
USB_TXIE_EP13
TX Endpoint 13 Interrupt Enable
13
14
USB_TXIE_EP14
TX Endpoint 14 Interrupt Enable
14
15
USB_TXIE_EP15
TX Endpoint 15 Interrupt Enable
15
16
USB_TXIE_EP2
TX Endpoint 2 Interrupt Enable
2
3
USB_TXIE_EP3
TX Endpoint 3 Interrupt Enable
3
4
USB_TXIE_EP4
TX Endpoint 4 Interrupt Enable
4
5
USB_TXIE_EP5
TX Endpoint 5 Interrupt Enable
5
6
USB_TXIE_EP6
TX Endpoint 6 Interrupt Enable
6
7
USB_TXIE_EP7
TX Endpoint 7 Interrupt Enable
7
8
USB_TXIE_EP8
TX Endpoint 8 Interrupt Enable
8
9
USB_TXIE_EP9
TX Endpoint 9 Interrupt Enable
9
10
USB0TXINTERVAL1
USB Host Transmit Interval Endpoint 1
0x11B
8
read-write
n
0x0
0x0
USB_TXINTERVAL1_TXPOLL
TX Polling
0
8
USB0TXINTERVAL10
USB Host Transmit Interval Endpoint 10
0x1AB
8
read-write
n
0x0
0x0
USB_TXINTERVAL10_TXPOLL
TX Polling
0
8
USB0TXINTERVAL11
USB Host Transmit Interval Endpoint 11
0x1BB
8
read-write
n
0x0
0x0
USB_TXINTERVAL11_TXPOLL
TX Polling
0
8
USB0TXINTERVAL12
USB Host Transmit Interval Endpoint 12
0x1CB
8
read-write
n
0x0
0x0
USB_TXINTERVAL12_TXPOLL
TX Polling
0
8
USB0TXINTERVAL13
USB Host Transmit Interval Endpoint 13
0x1DB
8
read-write
n
0x0
0x0
USB_TXINTERVAL13_TXPOLL
TX Polling
0
8
USB0TXINTERVAL14
USB Host Transmit Interval Endpoint 14
0x1EB
8
read-write
n
0x0
0x0
USB_TXINTERVAL14_TXPOLL
TX Polling
0
8
USB0TXINTERVAL15
USB Host Transmit Interval Endpoint 15
0x1FB
8
read-write
n
0x0
0x0
USB_TXINTERVAL15_TXPOLL
TX Polling
0
8
USB0TXINTERVAL2
USB Host Transmit Interval Endpoint 2
0x12B
8
read-write
n
0x0
0x0
USB_TXINTERVAL2_TXPOLL
TX Polling
0
8
USB0TXINTERVAL3
USB Host Transmit Interval Endpoint 3
0x13B
8
read-write
n
0x0
0x0
USB_TXINTERVAL3_TXPOLL
TX Polling
0
8
USB0TXINTERVAL4
USB Host Transmit Interval Endpoint 4
0x14B
8
read-write
n
0x0
0x0
USB_TXINTERVAL4_TXPOLL
TX Polling
0
8
USB0TXINTERVAL5
USB Host Transmit Interval Endpoint 5
0x15B
8
read-write
n
0x0
0x0
USB_TXINTERVAL5_TXPOLL
TX Polling
0
8
USB0TXINTERVAL6
USB Host Transmit Interval Endpoint 6
0x16B
8
read-write
n
0x0
0x0
USB_TXINTERVAL6_TXPOLL
TX Polling
0
8
USB0TXINTERVAL7
USB Host Transmit Interval Endpoint 7
0x17B
8
read-write
n
0x0
0x0
USB_TXINTERVAL7_TXPOLL
TX Polling
0
8
USB0TXINTERVAL8
USB Host Transmit Interval Endpoint 8
0x18B
8
read-write
n
0x0
0x0
USB_TXINTERVAL8_TXPOLL
TX Polling
0
8
USB0TXINTERVAL9
USB Host Transmit Interval Endpoint 9
0x19B
8
read-write
n
0x0
0x0
USB_TXINTERVAL9_TXPOLL
TX Polling
0
8
USB0TXIS
USB Transmit Interrupt Status
0x2
16
read-write
n
0x0
0x0
USB_TXIS_EP0
TX and RX Endpoint 0 Interrupt
0
1
USB_TXIS_EP1
TX Endpoint 1 Interrupt
1
2
USB_TXIS_EP10
TX Endpoint 10 Interrupt
10
11
USB_TXIS_EP11
TX Endpoint 11 Interrupt
11
12
USB_TXIS_EP12
TX Endpoint 12 Interrupt
12
13
USB_TXIS_EP13
TX Endpoint 13 Interrupt
13
14
USB_TXIS_EP14
TX Endpoint 14 Interrupt
14
15
USB_TXIS_EP15
TX Endpoint 15 Interrupt
15
16
USB_TXIS_EP2
TX Endpoint 2 Interrupt
2
3
USB_TXIS_EP3
TX Endpoint 3 Interrupt
3
4
USB_TXIS_EP4
TX Endpoint 4 Interrupt
4
5
USB_TXIS_EP5
TX Endpoint 5 Interrupt
5
6
USB_TXIS_EP6
TX Endpoint 6 Interrupt
6
7
USB_TXIS_EP7
TX Endpoint 7 Interrupt
7
8
USB_TXIS_EP8
TX Endpoint 8 Interrupt
8
9
USB_TXIS_EP9
TX Endpoint 9 Interrupt
9
10
USB0TXMAXP1
USB Maximum Transmit Data Endpoint 1
0x110
16
read-write
n
0x0
0x0
USB_TXMAXP1_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP10
USB Maximum Transmit Data Endpoint 10
0x1A0
16
read-write
n
0x0
0x0
USB_TXMAXP10_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP11
USB Maximum Transmit Data Endpoint 11
0x1B0
16
read-write
n
0x0
0x0
USB_TXMAXP11_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP12
USB Maximum Transmit Data Endpoint 12
0x1C0
16
read-write
n
0x0
0x0
USB_TXMAXP12_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP13
USB Maximum Transmit Data Endpoint 13
0x1D0
16
read-write
n
0x0
0x0
USB_TXMAXP13_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP14
USB Maximum Transmit Data Endpoint 14
0x1E0
16
read-write
n
0x0
0x0
USB_TXMAXP14_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP15
USB Maximum Transmit Data Endpoint 15
0x1F0
16
read-write
n
0x0
0x0
USB_TXMAXP15_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP2
USB Maximum Transmit Data Endpoint 2
0x120
16
read-write
n
0x0
0x0
USB_TXMAXP2_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP3
USB Maximum Transmit Data Endpoint 3
0x130
16
read-write
n
0x0
0x0
USB_TXMAXP3_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP4
USB Maximum Transmit Data Endpoint 4
0x140
16
read-write
n
0x0
0x0
USB_TXMAXP4_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP5
USB Maximum Transmit Data Endpoint 5
0x150
16
read-write
n
0x0
0x0
USB_TXMAXP5_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP6
USB Maximum Transmit Data Endpoint 6
0x160
16
read-write
n
0x0
0x0
USB_TXMAXP6_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP7
USB Maximum Transmit Data Endpoint 7
0x170
16
read-write
n
0x0
0x0
USB_TXMAXP7_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP8
USB Maximum Transmit Data Endpoint 8
0x180
16
read-write
n
0x0
0x0
USB_TXMAXP8_MAXLOAD
Maximum Payload
0
11
USB0TXMAXP9
USB Maximum Transmit Data Endpoint 9
0x190
16
read-write
n
0x0
0x0
USB_TXMAXP9_MAXLOAD
Maximum Payload
0
11
USB0TXTYPE1
USB Host Transmit Configure Type Endpoint 1
0x11A
8
read-write
n
0x0
0x0
USB_TXTYPE1_PROTO
Protocol
4
6
USB_TXTYPE1_PROTO_CTRL
Control
0x0
USB_TXTYPE1_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE1_PROTO_BULK
Bulk
0x2
USB_TXTYPE1_PROTO_INT
Interrupt
0x3
USB_TXTYPE1_SPEED
Operating Speed
6
8
USB_TXTYPE1_SPEED_DFLT
Default
0x0
USB_TXTYPE1_SPEED_FULL
Full
0x2
USB_TXTYPE1_SPEED_LOW
Low
0x3
USB_TXTYPE1_TEP
Target Endpoint Number
0
4
USB0TXTYPE10
USB Host Transmit Configure Type Endpoint 10
0x1AA
8
read-write
n
0x0
0x0
USB_TXTYPE10_PROTO
Protocol
4
6
USB_TXTYPE10_PROTO_CTRL
Control
0x0
USB_TXTYPE10_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE10_PROTO_BULK
Bulk
0x2
USB_TXTYPE10_PROTO_INT
Interrupt
0x3
USB_TXTYPE10_SPEED
Operating Speed
6
8
USB_TXTYPE10_SPEED_DFLT
Default
0x0
USB_TXTYPE10_SPEED_FULL
Full
0x2
USB_TXTYPE10_SPEED_LOW
Low
0x3
USB_TXTYPE10_TEP
Target Endpoint Number
0
4
USB0TXTYPE11
USB Host Transmit Configure Type Endpoint 11
0x1BA
8
read-write
n
0x0
0x0
USB_TXTYPE11_PROTO
Protocol
4
6
USB_TXTYPE11_PROTO_CTRL
Control
0x0
USB_TXTYPE11_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE11_PROTO_BULK
Bulk
0x2
USB_TXTYPE11_PROTO_INT
Interrupt
0x3
USB_TXTYPE11_SPEED
Operating Speed
6
8
USB_TXTYPE11_SPEED_DFLT
Default
0x0
USB_TXTYPE11_SPEED_FULL
Full
0x2
USB_TXTYPE11_SPEED_LOW
Low
0x3
USB_TXTYPE11_TEP
Target Endpoint Number
0
4
USB0TXTYPE12
USB Host Transmit Configure Type Endpoint 12
0x1CA
8
read-write
n
0x0
0x0
USB_TXTYPE12_PROTO
Protocol
4
6
USB_TXTYPE12_PROTO_CTRL
Control
0x0
USB_TXTYPE12_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE12_PROTO_BULK
Bulk
0x2
USB_TXTYPE12_PROTO_INT
Interrupt
0x3
USB_TXTYPE12_SPEED
Operating Speed
6
8
USB_TXTYPE12_SPEED_DFLT
Default
0x0
USB_TXTYPE12_SPEED_FULL
Full
0x2
USB_TXTYPE12_SPEED_LOW
Low
0x3
USB_TXTYPE12_TEP
Target Endpoint Number
0
4
USB0TXTYPE13
USB Host Transmit Configure Type Endpoint 13
0x1DA
8
read-write
n
0x0
0x0
USB_TXTYPE13_PROTO
Protocol
4
6
USB_TXTYPE13_PROTO_CTRL
Control
0x0
USB_TXTYPE13_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE13_PROTO_BULK
Bulk
0x2
USB_TXTYPE13_PROTO_INT
Interrupt
0x3
USB_TXTYPE13_SPEED
Operating Speed
6
8
USB_TXTYPE13_SPEED_DFLT
Default
0x0
USB_TXTYPE13_SPEED_FULL
Full
0x2
USB_TXTYPE13_SPEED_LOW
Low
0x3
USB_TXTYPE13_TEP
Target Endpoint Number
0
4
USB0TXTYPE14
USB Host Transmit Configure Type Endpoint 14
0x1EA
8
read-write
n
0x0
0x0
USB_TXTYPE14_PROTO
Protocol
4
6
USB_TXTYPE14_PROTO_CTRL
Control
0x0
USB_TXTYPE14_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE14_PROTO_BULK
Bulk
0x2
USB_TXTYPE14_PROTO_INT
Interrupt
0x3
USB_TXTYPE14_SPEED
Operating Speed
6
8
USB_TXTYPE14_SPEED_DFLT
Default
0x0
USB_TXTYPE14_SPEED_FULL
Full
0x2
USB_TXTYPE14_SPEED_LOW
Low
0x3
USB_TXTYPE14_TEP
Target Endpoint Number
0
4
USB0TXTYPE15
USB Host Transmit Configure Type Endpoint 15
0x1FA
8
read-write
n
0x0
0x0
USB_TXTYPE15_PROTO
Protocol
4
6
USB_TXTYPE15_PROTO_CTRL
Control
0x0
USB_TXTYPE15_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE15_PROTO_BULK
Bulk
0x2
USB_TXTYPE15_PROTO_INT
Interrupt
0x3
USB_TXTYPE15_SPEED
Operating Speed
6
8
USB_TXTYPE15_SPEED_DFLT
Default
0x0
USB_TXTYPE15_SPEED_FULL
Full
0x2
USB_TXTYPE15_SPEED_LOW
Low
0x3
USB_TXTYPE15_TEP
Target Endpoint Number
0
4
USB0TXTYPE2
USB Host Transmit Configure Type Endpoint 2
0x12A
8
read-write
n
0x0
0x0
USB_TXTYPE2_PROTO
Protocol
4
6
USB_TXTYPE2_PROTO_CTRL
Control
0x0
USB_TXTYPE2_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE2_PROTO_BULK
Bulk
0x2
USB_TXTYPE2_PROTO_INT
Interrupt
0x3
USB_TXTYPE2_SPEED
Operating Speed
6
8
USB_TXTYPE2_SPEED_DFLT
Default
0x0
USB_TXTYPE2_SPEED_FULL
Full
0x2
USB_TXTYPE2_SPEED_LOW
Low
0x3
USB_TXTYPE2_TEP
Target Endpoint Number
0
4
USB0TXTYPE3
USB Host Transmit Configure Type Endpoint 3
0x13A
8
read-write
n
0x0
0x0
USB_TXTYPE3_PROTO
Protocol
4
6
USB_TXTYPE3_PROTO_CTRL
Control
0x0
USB_TXTYPE3_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE3_PROTO_BULK
Bulk
0x2
USB_TXTYPE3_PROTO_INT
Interrupt
0x3
USB_TXTYPE3_SPEED
Operating Speed
6
8
USB_TXTYPE3_SPEED_DFLT
Default
0x0
USB_TXTYPE3_SPEED_FULL
Full
0x2
USB_TXTYPE3_SPEED_LOW
Low
0x3
USB_TXTYPE3_TEP
Target Endpoint Number
0
4
USB0TXTYPE4
USB Host Transmit Configure Type Endpoint 4
0x14A
8
read-write
n
0x0
0x0
USB_TXTYPE4_PROTO
Protocol
4
6
USB_TXTYPE4_PROTO_CTRL
Control
0x0
USB_TXTYPE4_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE4_PROTO_BULK
Bulk
0x2
USB_TXTYPE4_PROTO_INT
Interrupt
0x3
USB_TXTYPE4_SPEED
Operating Speed
6
8
USB_TXTYPE4_SPEED_DFLT
Default
0x0
USB_TXTYPE4_SPEED_FULL
Full
0x2
USB_TXTYPE4_SPEED_LOW
Low
0x3
USB_TXTYPE4_TEP
Target Endpoint Number
0
4
USB0TXTYPE5
USB Host Transmit Configure Type Endpoint 5
0x15A
8
read-write
n
0x0
0x0
USB_TXTYPE5_PROTO
Protocol
4
6
USB_TXTYPE5_PROTO_CTRL
Control
0x0
USB_TXTYPE5_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE5_PROTO_BULK
Bulk
0x2
USB_TXTYPE5_PROTO_INT
Interrupt
0x3
USB_TXTYPE5_SPEED
Operating Speed
6
8
USB_TXTYPE5_SPEED_DFLT
Default
0x0
USB_TXTYPE5_SPEED_FULL
Full
0x2
USB_TXTYPE5_SPEED_LOW
Low
0x3
USB_TXTYPE5_TEP
Target Endpoint Number
0
4
USB0TXTYPE6
USB Host Transmit Configure Type Endpoint 6
0x16A
8
read-write
n
0x0
0x0
USB_TXTYPE6_PROTO
Protocol
4
6
USB_TXTYPE6_PROTO_CTRL
Control
0x0
USB_TXTYPE6_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE6_PROTO_BULK
Bulk
0x2
USB_TXTYPE6_PROTO_INT
Interrupt
0x3
USB_TXTYPE6_SPEED
Operating Speed
6
8
USB_TXTYPE6_SPEED_DFLT
Default
0x0
USB_TXTYPE6_SPEED_FULL
Full
0x2
USB_TXTYPE6_SPEED_LOW
Low
0x3
USB_TXTYPE6_TEP
Target Endpoint Number
0
4
USB0TXTYPE7
USB Host Transmit Configure Type Endpoint 7
0x17A
8
read-write
n
0x0
0x0
USB_TXTYPE7_PROTO
Protocol
4
6
USB_TXTYPE7_PROTO_CTRL
Control
0x0
USB_TXTYPE7_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE7_PROTO_BULK
Bulk
0x2
USB_TXTYPE7_PROTO_INT
Interrupt
0x3
USB_TXTYPE7_SPEED
Operating Speed
6
8
USB_TXTYPE7_SPEED_DFLT
Default
0x0
USB_TXTYPE7_SPEED_FULL
Full
0x2
USB_TXTYPE7_SPEED_LOW
Low
0x3
USB_TXTYPE7_TEP
Target Endpoint Number
0
4
USB0TXTYPE8
USB Host Transmit Configure Type Endpoint 8
0x18A
8
read-write
n
0x0
0x0
USB_TXTYPE8_PROTO
Protocol
4
6
USB_TXTYPE8_PROTO_CTRL
Control
0x0
USB_TXTYPE8_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE8_PROTO_BULK
Bulk
0x2
USB_TXTYPE8_PROTO_INT
Interrupt
0x3
USB_TXTYPE8_SPEED
Operating Speed
6
8
USB_TXTYPE8_SPEED_DFLT
Default
0x0
USB_TXTYPE8_SPEED_FULL
Full
0x2
USB_TXTYPE8_SPEED_LOW
Low
0x3
USB_TXTYPE8_TEP
Target Endpoint Number
0
4
USB0TXTYPE9
USB Host Transmit Configure Type Endpoint 9
0x19A
8
read-write
n
0x0
0x0
USB_TXTYPE9_PROTO
Protocol
4
6
USB_TXTYPE9_PROTO_CTRL
Control
0x0
USB_TXTYPE9_PROTO_ISOC
Isochronous
0x1
USB_TXTYPE9_PROTO_BULK
Bulk
0x2
USB_TXTYPE9_PROTO_INT
Interrupt
0x3
USB_TXTYPE9_SPEED
Operating Speed
6
8
USB_TXTYPE9_SPEED_DFLT
Default
0x0
USB_TXTYPE9_SPEED_FULL
Full
0x2
USB_TXTYPE9_SPEED_LOW
Low
0x3
USB_TXTYPE9_TEP
Target Endpoint Number
0
4
USB0TYPE0
USB Type Endpoint 0
0x10A
8
read-write
n
0x0
0x0
USB_TYPE0_SPEED
Operating Speed
6
8
USB_TYPE0_SPEED_FULL
Full
0x2
USB_TYPE0_SPEED_LOW
Low
0x3
USB0VDC
USB VBUS Droop Control
0x430
read-write
n
0x0
0x0
USB_VDC_VBDEN
VBUS Droop Enable
0
1
USB0VDCIM
USB VBUS Droop Control Interrupt Mask
0x438
read-write
n
0x0
0x0
USB_VDCIM_VD
VBUS Droop Interrupt Mask
0
1
USB0VDCISC
USB VBUS Droop Control Interrupt Status and Clear
0x43C
read-write
n
0x0
0x0
USB_VDCISC_VD
VBUS Droop Interrupt Status and Clear
0
1
USB0VDCRIS
USB VBUS Droop Control Raw Interrupt Status
0x434
read-write
n
0x0
0x0
USB_VDCRIS_VD
VBUS Droop Raw Interrupt Status
0
1
USB0VPLEN
USB OTG VBUS Pulse Timing
0x7B
8
read-write
n
0x0
0x0
USB_VPLEN_VPLEN
VBUS Pulse Length
0
8
VDC
USB VBUS Droop Control
0x430
-1
read-write
n
0x0
0x0
USB_VDC_VBDEN
VBUS Droop Enable
0
1
VDCIM
USB VBUS Droop Control Interrupt Mask
0x438
-1
read-write
n
0x0
0x0
USB_VDCIM_VD
VBUS Droop Interrupt Mask
0
1
VDCISC
USB VBUS Droop Control Interrupt Status and Clear
0x43C
-1
read-write
n
0x0
0x0
USB_VDCISC_VD
VBUS Droop Interrupt Status and Clear
0
1
VDCRIS
USB VBUS Droop Control Raw Interrupt Status
0x434
-1
read-write
n
0x0
0x0
USB_VDCRIS_VD
VBUS Droop Raw Interrupt Status
0
1
VPLEN
USB OTG VBUS Pulse Timing
0x7B
8
read-write
n
0x0
0x0
USB_VPLEN_VPLEN
VBUS Pulse Length
0
8
WATCHDOG0
Register map for WATCHDOG0 peripheral
WATCHDOG
0x0
0x0
0x1000
registers
n
CTL
Watchdog Control
0x8
-1
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
WDT_CTL_WRC
Write Complete
31
32
ICR
Watchdog Interrupt Clear
0xC
-1
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
LOAD
Watchdog Load
0x0
-1
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
LOCK
Watchdog Lock
0xC00
-1
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
MIS
Watchdog Masked Interrupt Status
0x14
-1
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
RIS
Watchdog Raw Interrupt Status
0x10
-1
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
TEST
Watchdog Test
0x418
-1
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
VALUE
Watchdog Value
0x4
-1
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32
WATCHDOG0CTL
Watchdog Control
0x8
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
WDT_CTL_WRC
Write Complete
31
32
WATCHDOG0ICR
Watchdog Interrupt Clear
0xC
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
WATCHDOG0LOAD
Watchdog Load
0x0
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
WATCHDOG0LOCK
Watchdog Lock
0xC00
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
WATCHDOG0MIS
Watchdog Masked Interrupt Status
0x14
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
WATCHDOG0RIS
Watchdog Raw Interrupt Status
0x10
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
WATCHDOG0TEST
Watchdog Test
0x418
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
WATCHDOG0VALUE
Watchdog Value
0x4
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32
WATCHDOG1
Register map for WATCHDOG0 peripheral
WATCHDOG
0x0
0x0
0x1000
registers
n
CTL
Watchdog Control
0x8
-1
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
WDT_CTL_WRC
Write Complete
31
32
ICR
Watchdog Interrupt Clear
0xC
-1
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
LOAD
Watchdog Load
0x0
-1
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
LOCK
Watchdog Lock
0xC00
-1
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
MIS
Watchdog Masked Interrupt Status
0x14
-1
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
RIS
Watchdog Raw Interrupt Status
0x10
-1
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
TEST
Watchdog Test
0x418
-1
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
VALUE
Watchdog Value
0x4
-1
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32
WATCHDOG0CTL
Watchdog Control
0x8
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
WDT_CTL_WRC
Write Complete
31
32
WATCHDOG0ICR
Watchdog Interrupt Clear
0xC
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
WATCHDOG0LOAD
Watchdog Load
0x0
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
WATCHDOG0LOCK
Watchdog Lock
0xC00
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
WATCHDOG0MIS
Watchdog Masked Interrupt Status
0x14
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
WATCHDOG0RIS
Watchdog Raw Interrupt Status
0x10
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
WATCHDOG0TEST
Watchdog Test
0x418
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
WATCHDOG0VALUE
Watchdog Value
0x4
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32